RTOS 1.0
stm32f412vx.h
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33#ifndef __STM32F412Vx_H
34#define __STM32F412Vx_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
43
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
52
56
60
65typedef enum
66{
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
95 ADC_IRQn = 18,
148 RNG_IRQn = 80,
149 FPU_IRQn = 81,
155} IRQn_Type;
156
160
161#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
162#include "system_stm32f4xx.h"
163#include <stdint.h>
164
168
172
173typedef struct
174{
175 __IO uint32_t SR;
176 __IO uint32_t CR1;
177 __IO uint32_t CR2;
178 __IO uint32_t SMPR1;
179 __IO uint32_t SMPR2;
180 __IO uint32_t JOFR1;
181 __IO uint32_t JOFR2;
182 __IO uint32_t JOFR3;
183 __IO uint32_t JOFR4;
184 __IO uint32_t HTR;
185 __IO uint32_t LTR;
186 __IO uint32_t SQR1;
187 __IO uint32_t SQR2;
188 __IO uint32_t SQR3;
189 __IO uint32_t JSQR;
190 __IO uint32_t JDR1;
191 __IO uint32_t JDR2;
192 __IO uint32_t JDR3;
193 __IO uint32_t JDR4;
194 __IO uint32_t DR;
196
197typedef struct
198{
199 __IO uint32_t CSR;
200 __IO uint32_t CCR;
201 __IO uint32_t CDR;
204
205
209
210typedef struct
211{
212 __IO uint32_t TIR;
213 __IO uint32_t TDTR;
214 __IO uint32_t TDLR;
215 __IO uint32_t TDHR;
217
221
222typedef struct
223{
224 __IO uint32_t RIR;
225 __IO uint32_t RDTR;
226 __IO uint32_t RDLR;
227 __IO uint32_t RDHR;
229
233
234typedef struct
235{
236 __IO uint32_t FR1;
237 __IO uint32_t FR2;
239
243
244typedef struct
245{
246 __IO uint32_t MCR;
247 __IO uint32_t MSR;
248 __IO uint32_t TSR;
249 __IO uint32_t RF0R;
250 __IO uint32_t RF1R;
251 __IO uint32_t IER;
252 __IO uint32_t ESR;
253 __IO uint32_t BTR;
254 uint32_t RESERVED0[88];
255 CAN_TxMailBox_TypeDef sTxMailBox[3];
256 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
257 uint32_t RESERVED1[12];
258 __IO uint32_t FMR;
259 __IO uint32_t FM1R;
260 uint32_t RESERVED2;
261 __IO uint32_t FS1R;
262 uint32_t RESERVED3;
263 __IO uint32_t FFA1R;
264 uint32_t RESERVED4;
265 __IO uint32_t FA1R;
266 uint32_t RESERVED5[8];
267 CAN_FilterRegister_TypeDef sFilterRegister[28];
269
273
274typedef struct
275{
276 __IO uint32_t DR;
277 __IO uint8_t IDR;
278 uint8_t RESERVED0;
279 uint16_t RESERVED1;
280 __IO uint32_t CR;
282
286typedef struct
287{
288 __IO uint32_t FLTCR1;
289 __IO uint32_t FLTCR2;
290 __IO uint32_t FLTISR;
291 __IO uint32_t FLTICR;
292 __IO uint32_t FLTJCHGR;
293 __IO uint32_t FLTFCR;
294 __IO uint32_t FLTJDATAR;
295 __IO uint32_t FLTRDATAR;
296 __IO uint32_t FLTAWHTR;
297 __IO uint32_t FLTAWLTR;
298 __IO uint32_t FLTAWSR;
299 __IO uint32_t FLTAWCFR;
300 __IO uint32_t FLTEXMAX;
301 __IO uint32_t FLTEXMIN;
302 __IO uint32_t FLTCNVTIMR;
304
308typedef struct
309{
310 __IO uint32_t CHCFGR1;
311 __IO uint32_t CHCFGR2;
312 __IO uint32_t CHAWSCDR;
314 __IO uint32_t CHWDATAR;
315 __IO uint32_t CHDATINR;
317
321
322typedef struct
323{
324 __IO uint32_t IDCODE;
325 __IO uint32_t CR;
326 __IO uint32_t APB1FZ;
327 __IO uint32_t APB2FZ;
329
330
334
335typedef struct
336{
337 __IO uint32_t CR;
338 __IO uint32_t NDTR;
339 __IO uint32_t PAR;
340 __IO uint32_t M0AR;
341 __IO uint32_t M1AR;
342 __IO uint32_t FCR;
344
345typedef struct
346{
347 __IO uint32_t LISR;
348 __IO uint32_t HISR;
349 __IO uint32_t LIFCR;
350 __IO uint32_t HIFCR;
352
356
357typedef struct
358{
359 __IO uint32_t IMR;
360 __IO uint32_t EMR;
361 __IO uint32_t RTSR;
362 __IO uint32_t FTSR;
363 __IO uint32_t SWIER;
364 __IO uint32_t PR;
366
370
371typedef struct
372{
373 __IO uint32_t ACR;
374 __IO uint32_t KEYR;
375 __IO uint32_t OPTKEYR;
376 __IO uint32_t SR;
377 __IO uint32_t CR;
378 __IO uint32_t OPTCR;
379 __IO uint32_t OPTCR1;
381
382
383
387
388typedef struct
389{
390 __IO uint32_t BTCR[8];
392
396
397typedef struct
398{
399 __IO uint32_t BWTR[7];
404
405typedef struct
406{
407 __IO uint32_t MODER;
408 __IO uint32_t OTYPER;
409 __IO uint32_t OSPEEDR;
410 __IO uint32_t PUPDR;
411 __IO uint32_t IDR;
412 __IO uint32_t ODR;
413 __IO uint32_t BSRR;
414 __IO uint32_t LCKR;
415 __IO uint32_t AFR[2];
417
421
422typedef struct
423{
424 __IO uint32_t MEMRMP;
425 __IO uint32_t PMC;
426 __IO uint32_t EXTICR[4];
427 uint32_t RESERVED;
428 __IO uint32_t CFGR2;
429 __IO uint32_t CMPCR;
430 __IO uint32_t CFGR;
432
436
437typedef struct
438{
439 __IO uint32_t CR1;
440 __IO uint32_t CR2;
441 __IO uint32_t OAR1;
442 __IO uint32_t OAR2;
443 __IO uint32_t DR;
444 __IO uint32_t SR1;
445 __IO uint32_t SR2;
446 __IO uint32_t CCR;
447 __IO uint32_t TRISE;
448 __IO uint32_t FLTR;
450
454
455typedef struct
456{
457 __IO uint32_t CR1;
458 __IO uint32_t CR2;
459 __IO uint32_t OAR1;
460 __IO uint32_t OAR2;
461 __IO uint32_t TIMINGR;
462 __IO uint32_t TIMEOUTR;
463 __IO uint32_t ISR;
464 __IO uint32_t ICR;
465 __IO uint32_t PECR;
466 __IO uint32_t RXDR;
467 __IO uint32_t TXDR;
469
473
474typedef struct
475{
476 __IO uint32_t KR;
477 __IO uint32_t PR;
478 __IO uint32_t RLR;
479 __IO uint32_t SR;
481
482
486
487typedef struct
488{
489 __IO uint32_t CR;
490 __IO uint32_t CSR;
492
496
497typedef struct
498{
499 __IO uint32_t CR;
500 __IO uint32_t PLLCFGR;
501 __IO uint32_t CFGR;
502 __IO uint32_t CIR;
503 __IO uint32_t AHB1RSTR;
504 __IO uint32_t AHB2RSTR;
505 __IO uint32_t AHB3RSTR;
506 uint32_t RESERVED0;
507 __IO uint32_t APB1RSTR;
508 __IO uint32_t APB2RSTR;
509 uint32_t RESERVED1[2];
510 __IO uint32_t AHB1ENR;
511 __IO uint32_t AHB2ENR;
512 __IO uint32_t AHB3ENR;
513 uint32_t RESERVED2;
514 __IO uint32_t APB1ENR;
515 __IO uint32_t APB2ENR;
516 uint32_t RESERVED3[2];
517 __IO uint32_t AHB1LPENR;
518 __IO uint32_t AHB2LPENR;
519 __IO uint32_t AHB3LPENR;
520 uint32_t RESERVED4;
521 __IO uint32_t APB1LPENR;
522 __IO uint32_t APB2LPENR;
523 uint32_t RESERVED5[2];
524 __IO uint32_t BDCR;
525 __IO uint32_t CSR;
526 uint32_t RESERVED6[2];
527 __IO uint32_t SSCGR;
528 __IO uint32_t PLLI2SCFGR;
529 uint32_t RESERVED7;
530 __IO uint32_t DCKCFGR;
531 __IO uint32_t CKGATENR;
532 __IO uint32_t DCKCFGR2;
534
538
539typedef struct
540{
541 __IO uint32_t TR;
542 __IO uint32_t DR;
543 __IO uint32_t CR;
544 __IO uint32_t ISR;
545 __IO uint32_t PRER;
546 __IO uint32_t WUTR;
547 __IO uint32_t CALIBR;
548 __IO uint32_t ALRMAR;
549 __IO uint32_t ALRMBR;
550 __IO uint32_t WPR;
551 __IO uint32_t SSR;
552 __IO uint32_t SHIFTR;
553 __IO uint32_t TSTR;
554 __IO uint32_t TSDR;
555 __IO uint32_t TSSSR;
556 __IO uint32_t CALR;
557 __IO uint32_t TAFCR;
558 __IO uint32_t ALRMASSR;
559 __IO uint32_t ALRMBSSR;
560 uint32_t RESERVED7;
561 __IO uint32_t BKP0R;
562 __IO uint32_t BKP1R;
563 __IO uint32_t BKP2R;
564 __IO uint32_t BKP3R;
565 __IO uint32_t BKP4R;
566 __IO uint32_t BKP5R;
567 __IO uint32_t BKP6R;
568 __IO uint32_t BKP7R;
569 __IO uint32_t BKP8R;
570 __IO uint32_t BKP9R;
571 __IO uint32_t BKP10R;
572 __IO uint32_t BKP11R;
573 __IO uint32_t BKP12R;
574 __IO uint32_t BKP13R;
575 __IO uint32_t BKP14R;
576 __IO uint32_t BKP15R;
577 __IO uint32_t BKP16R;
578 __IO uint32_t BKP17R;
579 __IO uint32_t BKP18R;
580 __IO uint32_t BKP19R;
582
586
587typedef struct
588{
589 __IO uint32_t POWER;
590 __IO uint32_t CLKCR;
591 __IO uint32_t ARG;
592 __IO uint32_t CMD;
593 __IO const uint32_t RESPCMD;
594 __IO const uint32_t RESP1;
595 __IO const uint32_t RESP2;
596 __IO const uint32_t RESP3;
597 __IO const uint32_t RESP4;
598 __IO uint32_t DTIMER;
599 __IO uint32_t DLEN;
600 __IO uint32_t DCTRL;
601 __IO const uint32_t DCOUNT;
602 __IO const uint32_t STA;
603 __IO uint32_t ICR;
604 __IO uint32_t MASK;
605 uint32_t RESERVED0[2];
606 __IO const uint32_t FIFOCNT;
607 uint32_t RESERVED1[13];
608 __IO uint32_t FIFO;
610
614
615typedef struct
616{
617 __IO uint32_t CR1;
618 __IO uint32_t CR2;
619 __IO uint32_t SR;
620 __IO uint32_t DR;
621 __IO uint32_t CRCPR;
622 __IO uint32_t RXCRCR;
623 __IO uint32_t TXCRCR;
624 __IO uint32_t I2SCFGR;
625 __IO uint32_t I2SPR;
627
631
632typedef struct
633{
634 __IO uint32_t CR;
635 __IO uint32_t DCR;
636 __IO uint32_t SR;
637 __IO uint32_t FCR;
638 __IO uint32_t DLR;
639 __IO uint32_t CCR;
640 __IO uint32_t AR;
641 __IO uint32_t ABR;
642 __IO uint32_t DR;
643 __IO uint32_t PSMKR;
644 __IO uint32_t PSMAR;
645 __IO uint32_t PIR;
646 __IO uint32_t LPTR;
648
652
653typedef struct
654{
655 __IO uint32_t CR1;
656 __IO uint32_t CR2;
657 __IO uint32_t SMCR;
658 __IO uint32_t DIER;
659 __IO uint32_t SR;
660 __IO uint32_t EGR;
661 __IO uint32_t CCMR1;
662 __IO uint32_t CCMR2;
663 __IO uint32_t CCER;
664 __IO uint32_t CNT;
665 __IO uint32_t PSC;
666 __IO uint32_t ARR;
667 __IO uint32_t RCR;
668 __IO uint32_t CCR1;
669 __IO uint32_t CCR2;
670 __IO uint32_t CCR3;
671 __IO uint32_t CCR4;
672 __IO uint32_t BDTR;
673 __IO uint32_t DCR;
674 __IO uint32_t DMAR;
675 __IO uint32_t OR;
677
681
682typedef struct
683{
684 __IO uint32_t SR;
685 __IO uint32_t DR;
686 __IO uint32_t BRR;
687 __IO uint32_t CR1;
688 __IO uint32_t CR2;
689 __IO uint32_t CR3;
690 __IO uint32_t GTPR;
692
696
697typedef struct
698{
699 __IO uint32_t CR;
700 __IO uint32_t CFR;
701 __IO uint32_t SR;
703
707
708typedef struct
709{
710 __IO uint32_t CR;
711 __IO uint32_t SR;
712 __IO uint32_t DR;
714
718typedef struct
719{
720 __IO uint32_t GOTGCTL;
721 __IO uint32_t GOTGINT;
722 __IO uint32_t GAHBCFG;
723 __IO uint32_t GUSBCFG;
724 __IO uint32_t GRSTCTL;
725 __IO uint32_t GINTSTS;
726 __IO uint32_t GINTMSK;
727 __IO uint32_t GRXSTSR;
728 __IO uint32_t GRXSTSP;
729 __IO uint32_t GRXFSIZ;
730 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
731 __IO uint32_t HNPTXSTS;
732 uint32_t Reserved30[2];
733 __IO uint32_t GCCFG;
734 __IO uint32_t CID;
735 uint32_t Reserved5[3];
736 __IO uint32_t GHWCFG3;
737 uint32_t Reserved6;
738 __IO uint32_t GLPMCFG;
739 uint32_t Reserved;
740 __IO uint32_t GDFIFOCFG;
741 uint32_t Reserved43[40];
742 __IO uint32_t HPTXFSIZ;
743 __IO uint32_t DIEPTXF[0x0F];
745
749typedef struct
750{
751 __IO uint32_t DCFG;
752 __IO uint32_t DCTL;
753 __IO uint32_t DSTS;
754 uint32_t Reserved0C;
755 __IO uint32_t DIEPMSK;
756 __IO uint32_t DOEPMSK;
757 __IO uint32_t DAINT;
758 __IO uint32_t DAINTMSK;
759 uint32_t Reserved20;
760 uint32_t Reserved9;
761 __IO uint32_t DVBUSDIS;
762 __IO uint32_t DVBUSPULSE;
763 __IO uint32_t DTHRCTL;
764 __IO uint32_t DIEPEMPMSK;
765 __IO uint32_t DEACHINT;
766 __IO uint32_t DEACHMSK;
767 uint32_t Reserved40;
768 __IO uint32_t DINEP1MSK;
769 uint32_t Reserved44[15];
770 __IO uint32_t DOUTEP1MSK;
772
776typedef struct
777{
778 __IO uint32_t DIEPCTL;
779 uint32_t Reserved04;
780 __IO uint32_t DIEPINT;
781 uint32_t Reserved0C;
782 __IO uint32_t DIEPTSIZ;
783 __IO uint32_t DIEPDMA;
784 __IO uint32_t DTXFSTS;
785 uint32_t Reserved18;
787
791typedef struct
792{
793 __IO uint32_t DOEPCTL;
794 uint32_t Reserved04;
795 __IO uint32_t DOEPINT;
796 uint32_t Reserved0C;
797 __IO uint32_t DOEPTSIZ;
798 __IO uint32_t DOEPDMA;
799 uint32_t Reserved18[2];
801
805typedef struct
806{
807 __IO uint32_t HCFG;
808 __IO uint32_t HFIR;
809 __IO uint32_t HFNUM;
810 uint32_t Reserved40C;
811 __IO uint32_t HPTXSTS;
812 __IO uint32_t HAINT;
813 __IO uint32_t HAINTMSK;
815
819typedef struct
820{
821 __IO uint32_t HCCHAR;
822 __IO uint32_t HCSPLT;
823 __IO uint32_t HCINT;
824 __IO uint32_t HCINTMSK;
825 __IO uint32_t HCTSIZ;
826 __IO uint32_t HCDMA;
827 uint32_t Reserved[2];
829
833
837#define FLASH_BASE 0x08000000UL
838#define SRAM1_BASE 0x20000000UL
839#define PERIPH_BASE 0x40000000UL
840#define FSMC_R_BASE 0xA0000000UL
841#define QSPI_R_BASE 0xA0001000UL
842#define SRAM1_BB_BASE 0x22000000UL
843#define PERIPH_BB_BASE 0x42000000UL
844#define FLASH_END 0x080FFFFFUL
845#define FLASH_OTP_BASE 0x1FFF7800UL
846#define FLASH_OTP_END 0x1FFF7A0FUL
847
848/* Legacy defines */
849#define SRAM_BASE SRAM1_BASE
850#define SRAM_BB_BASE SRAM1_BB_BASE
851
853#define APB1PERIPH_BASE PERIPH_BASE
854#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
855#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
856#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
857
859#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
860#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
861#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
862#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
863#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
864#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
865#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
866#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
867#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
868#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
869#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
870#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
871#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
872#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
873#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
874#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
875#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
876#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
877#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
878#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
879#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
880#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL)
881#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
882#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
883#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
884
886#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
887#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
888#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
889#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
890#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
891#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
892/* Legacy define */
893#define ADC_BASE ADC1_COMMON_BASE
894#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
895#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
896#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
897#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
898#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
899#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
900#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
901#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
902#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
903#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
904#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
905#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
906#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
907#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
908#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
909#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
910
912#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
913#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
914#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
915#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
916#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
917#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
918#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
919#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
920#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
921#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
922#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
923#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
924#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
925#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
926#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
927#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
928#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
929#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
930#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
931#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
932#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
933#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
934#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
935#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
936#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
937#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
938#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
939
941#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
942
943
945#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
946#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
947
949#define DBGMCU_BASE 0xE0042000UL
951#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
952
953#define USB_OTG_GLOBAL_BASE 0x000UL
954#define USB_OTG_DEVICE_BASE 0x800UL
955#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
956#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
957#define USB_OTG_EP_REG_SIZE 0x20UL
958#define USB_OTG_HOST_BASE 0x400UL
959#define USB_OTG_HOST_PORT_BASE 0x440UL
960#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
961#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
962#define USB_OTG_PCGCCTL_BASE 0xE00UL
963#define USB_OTG_FIFO_BASE 0x1000UL
964#define USB_OTG_FIFO_SIZE 0x1000UL
965
966#define UID_BASE 0x1FFF7A10UL
967#define FLASHSIZE_BASE 0x1FFF7A22UL
968#define PACKAGE_BASE 0x1FFF7BF0UL
972
976#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
977#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
978#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
979#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
980#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
981#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
982#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
983#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
984#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
985#define RTC ((RTC_TypeDef *) RTC_BASE)
986#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
987#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
988#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
989#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
990#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
991#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
992#define USART2 ((USART_TypeDef *) USART2_BASE)
993#define USART3 ((USART_TypeDef *) USART3_BASE)
994#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
995#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
996#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
997#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
998#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
999#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1000#define PWR ((PWR_TypeDef *) PWR_BASE)
1001#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1002#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1003#define USART1 ((USART_TypeDef *) USART1_BASE)
1004#define USART6 ((USART_TypeDef *) USART6_BASE)
1005#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1006#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1007/* Legacy define */
1008#define ADC ADC1_COMMON
1009#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1010#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1011#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1012#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1013#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1014#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1015#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1016#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1017#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1018#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1019#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1020#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1021#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1022#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1023#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1024#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1025#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1026#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1027#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1028#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1029#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1030#define CRC ((CRC_TypeDef *) CRC_BASE)
1031#define RCC ((RCC_TypeDef *) RCC_BASE)
1032#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1033#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1034#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1035#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1036#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1037#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1038#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1039#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1040#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1041#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1042#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1043#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1044#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1045#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1046#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1047#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1048#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1049#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1050#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1051#define RNG ((RNG_TypeDef *) RNG_BASE)
1052#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1053#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1054#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1055#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1056#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1057
1061
1065
1069#define LSI_STARTUP_TIME 40U
1073
1077
1078/******************************************************************************/
1079/* Peripheral Registers_Bits_Definition */
1080/******************************************************************************/
1081
1082/******************************************************************************/
1083/* */
1084/* Analog to Digital Converter */
1085/* */
1086/******************************************************************************/
1087
1088/******************** Bit definition for ADC_SR register ********************/
1089#define ADC_SR_AWD_Pos (0U)
1090#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1091#define ADC_SR_AWD ADC_SR_AWD_Msk
1092#define ADC_SR_EOC_Pos (1U)
1093#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1094#define ADC_SR_EOC ADC_SR_EOC_Msk
1095#define ADC_SR_JEOC_Pos (2U)
1096#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1097#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1098#define ADC_SR_JSTRT_Pos (3U)
1099#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1100#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1101#define ADC_SR_STRT_Pos (4U)
1102#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1103#define ADC_SR_STRT ADC_SR_STRT_Msk
1104#define ADC_SR_OVR_Pos (5U)
1105#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1106#define ADC_SR_OVR ADC_SR_OVR_Msk
1107
1108/******************* Bit definition for ADC_CR1 register ********************/
1109#define ADC_CR1_AWDCH_Pos (0U)
1110#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1111#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1112#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1113#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1114#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1115#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1116#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1117#define ADC_CR1_EOCIE_Pos (5U)
1118#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1119#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1120#define ADC_CR1_AWDIE_Pos (6U)
1121#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1122#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1123#define ADC_CR1_JEOCIE_Pos (7U)
1124#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1125#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1126#define ADC_CR1_SCAN_Pos (8U)
1127#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1128#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1129#define ADC_CR1_AWDSGL_Pos (9U)
1130#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1131#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1132#define ADC_CR1_JAUTO_Pos (10U)
1133#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1134#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1135#define ADC_CR1_DISCEN_Pos (11U)
1136#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1137#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1138#define ADC_CR1_JDISCEN_Pos (12U)
1139#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1140#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1141#define ADC_CR1_DISCNUM_Pos (13U)
1142#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1143#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1144#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1145#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1146#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1147#define ADC_CR1_JAWDEN_Pos (22U)
1148#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1149#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1150#define ADC_CR1_AWDEN_Pos (23U)
1151#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1152#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1153#define ADC_CR1_RES_Pos (24U)
1154#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1155#define ADC_CR1_RES ADC_CR1_RES_Msk
1156#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1157#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1158#define ADC_CR1_OVRIE_Pos (26U)
1159#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1160#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1161
1162/******************* Bit definition for ADC_CR2 register ********************/
1163#define ADC_CR2_ADON_Pos (0U)
1164#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1165#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1166#define ADC_CR2_CONT_Pos (1U)
1167#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1168#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1169#define ADC_CR2_DMA_Pos (8U)
1170#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1171#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1172#define ADC_CR2_DDS_Pos (9U)
1173#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1174#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1175#define ADC_CR2_EOCS_Pos (10U)
1176#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1177#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1178#define ADC_CR2_ALIGN_Pos (11U)
1179#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1180#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1181#define ADC_CR2_JEXTSEL_Pos (16U)
1182#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1183#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1184#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1185#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1186#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1187#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1188#define ADC_CR2_JEXTEN_Pos (20U)
1189#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1190#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1191#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1192#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1193#define ADC_CR2_JSWSTART_Pos (22U)
1194#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1195#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1196#define ADC_CR2_EXTSEL_Pos (24U)
1197#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1198#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1199#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1200#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1201#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1202#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1203#define ADC_CR2_EXTEN_Pos (28U)
1204#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1205#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1206#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1207#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1208#define ADC_CR2_SWSTART_Pos (30U)
1209#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1210#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1211
1212/****************** Bit definition for ADC_SMPR1 register *******************/
1213#define ADC_SMPR1_SMP10_Pos (0U)
1214#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1215#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1216#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1217#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1218#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1219#define ADC_SMPR1_SMP11_Pos (3U)
1220#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1221#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1222#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1223#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1224#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1225#define ADC_SMPR1_SMP12_Pos (6U)
1226#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1227#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1228#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1229#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1230#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1231#define ADC_SMPR1_SMP13_Pos (9U)
1232#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1233#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1234#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1235#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1236#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1237#define ADC_SMPR1_SMP14_Pos (12U)
1238#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1239#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1240#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1241#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1242#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1243#define ADC_SMPR1_SMP15_Pos (15U)
1244#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1245#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1246#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1247#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1248#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1249#define ADC_SMPR1_SMP16_Pos (18U)
1250#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1251#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1252#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1253#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1254#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1255#define ADC_SMPR1_SMP17_Pos (21U)
1256#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1257#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1258#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1259#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1260#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1261#define ADC_SMPR1_SMP18_Pos (24U)
1262#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1263#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1264#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1265#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1266#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1267
1268/****************** Bit definition for ADC_SMPR2 register *******************/
1269#define ADC_SMPR2_SMP0_Pos (0U)
1270#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1271#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1272#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1273#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1274#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1275#define ADC_SMPR2_SMP1_Pos (3U)
1276#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1277#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1278#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1279#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1280#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1281#define ADC_SMPR2_SMP2_Pos (6U)
1282#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1283#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1284#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1285#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1286#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1287#define ADC_SMPR2_SMP3_Pos (9U)
1288#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1289#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1290#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1291#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1292#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1293#define ADC_SMPR2_SMP4_Pos (12U)
1294#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1295#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1296#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1297#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1298#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1299#define ADC_SMPR2_SMP5_Pos (15U)
1300#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1301#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1302#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1303#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1304#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1305#define ADC_SMPR2_SMP6_Pos (18U)
1306#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1307#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1308#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1309#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1310#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1311#define ADC_SMPR2_SMP7_Pos (21U)
1312#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1313#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1314#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1315#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1316#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1317#define ADC_SMPR2_SMP8_Pos (24U)
1318#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1319#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1320#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1321#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1322#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1323#define ADC_SMPR2_SMP9_Pos (27U)
1324#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1325#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1326#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1327#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1328#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1329
1330/****************** Bit definition for ADC_JOFR1 register *******************/
1331#define ADC_JOFR1_JOFFSET1_Pos (0U)
1332#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1333#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1334
1335/****************** Bit definition for ADC_JOFR2 register *******************/
1336#define ADC_JOFR2_JOFFSET2_Pos (0U)
1337#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1338#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1339
1340/****************** Bit definition for ADC_JOFR3 register *******************/
1341#define ADC_JOFR3_JOFFSET3_Pos (0U)
1342#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1343#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1344
1345/****************** Bit definition for ADC_JOFR4 register *******************/
1346#define ADC_JOFR4_JOFFSET4_Pos (0U)
1347#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1348#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1349
1350/******************* Bit definition for ADC_HTR register ********************/
1351#define ADC_HTR_HT_Pos (0U)
1352#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1353#define ADC_HTR_HT ADC_HTR_HT_Msk
1354
1355/******************* Bit definition for ADC_LTR register ********************/
1356#define ADC_LTR_LT_Pos (0U)
1357#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1358#define ADC_LTR_LT ADC_LTR_LT_Msk
1359
1360/******************* Bit definition for ADC_SQR1 register *******************/
1361#define ADC_SQR1_SQ13_Pos (0U)
1362#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1363#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1364#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1365#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1366#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1367#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1368#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1369#define ADC_SQR1_SQ14_Pos (5U)
1370#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1371#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1372#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1373#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1374#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1375#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1376#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1377#define ADC_SQR1_SQ15_Pos (10U)
1378#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1379#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1380#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1381#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1382#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1383#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1384#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1385#define ADC_SQR1_SQ16_Pos (15U)
1386#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1387#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1388#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1389#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1390#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1391#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1392#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1393#define ADC_SQR1_L_Pos (20U)
1394#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1395#define ADC_SQR1_L ADC_SQR1_L_Msk
1396#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1397#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1398#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1399#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1400
1401/******************* Bit definition for ADC_SQR2 register *******************/
1402#define ADC_SQR2_SQ7_Pos (0U)
1403#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1404#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1405#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1406#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1407#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1408#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1409#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1410#define ADC_SQR2_SQ8_Pos (5U)
1411#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1412#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1413#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1414#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1415#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1416#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1417#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1418#define ADC_SQR2_SQ9_Pos (10U)
1419#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1420#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1421#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1422#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1423#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1424#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1425#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1426#define ADC_SQR2_SQ10_Pos (15U)
1427#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1428#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1429#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1430#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1431#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1432#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1433#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1434#define ADC_SQR2_SQ11_Pos (20U)
1435#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1436#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1437#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1438#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1439#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1440#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1441#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1442#define ADC_SQR2_SQ12_Pos (25U)
1443#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1444#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1445#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1446#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1447#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1448#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1449#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1450
1451/******************* Bit definition for ADC_SQR3 register *******************/
1452#define ADC_SQR3_SQ1_Pos (0U)
1453#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1454#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1455#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1456#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1457#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1458#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1459#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1460#define ADC_SQR3_SQ2_Pos (5U)
1461#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1462#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1463#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1464#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1465#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1466#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1467#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1468#define ADC_SQR3_SQ3_Pos (10U)
1469#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1470#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1471#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1472#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1473#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1474#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1475#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1476#define ADC_SQR3_SQ4_Pos (15U)
1477#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1478#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1479#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1480#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1481#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1482#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1483#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1484#define ADC_SQR3_SQ5_Pos (20U)
1485#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1486#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1487#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1488#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1489#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1490#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1491#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1492#define ADC_SQR3_SQ6_Pos (25U)
1493#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1494#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1495#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1496#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1497#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1498#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1499#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1500
1501/******************* Bit definition for ADC_JSQR register *******************/
1502#define ADC_JSQR_JSQ1_Pos (0U)
1503#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1504#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1505#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1506#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1507#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1508#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1509#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1510#define ADC_JSQR_JSQ2_Pos (5U)
1511#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1512#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1513#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1514#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1515#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1516#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1517#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1518#define ADC_JSQR_JSQ3_Pos (10U)
1519#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1520#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1521#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1522#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1523#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1524#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1525#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1526#define ADC_JSQR_JSQ4_Pos (15U)
1527#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1528#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1529#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1530#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1531#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1532#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1533#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1534#define ADC_JSQR_JL_Pos (20U)
1535#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1536#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1537#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1538#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1539
1540/******************* Bit definition for ADC_JDR1 register *******************/
1541#define ADC_JDR1_JDATA_Pos (0U)
1542#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1543#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1544
1545/******************* Bit definition for ADC_JDR2 register *******************/
1546#define ADC_JDR2_JDATA_Pos (0U)
1547#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1548#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1549
1550/******************* Bit definition for ADC_JDR3 register *******************/
1551#define ADC_JDR3_JDATA_Pos (0U)
1552#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1553#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1554
1555/******************* Bit definition for ADC_JDR4 register *******************/
1556#define ADC_JDR4_JDATA_Pos (0U)
1557#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1558#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1559
1560/******************** Bit definition for ADC_DR register ********************/
1561#define ADC_DR_DATA_Pos (0U)
1562#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1563#define ADC_DR_DATA ADC_DR_DATA_Msk
1564#define ADC_DR_ADC2DATA_Pos (16U)
1565#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1566#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1567
1568/******************* Bit definition for ADC_CSR register ********************/
1569#define ADC_CSR_AWD1_Pos (0U)
1570#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1571#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1572#define ADC_CSR_EOC1_Pos (1U)
1573#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1574#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1575#define ADC_CSR_JEOC1_Pos (2U)
1576#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1577#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1578#define ADC_CSR_JSTRT1_Pos (3U)
1579#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1580#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1581#define ADC_CSR_STRT1_Pos (4U)
1582#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1583#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1584#define ADC_CSR_OVR1_Pos (5U)
1585#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1586#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1587
1588/* Legacy defines */
1589#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1590
1591/******************* Bit definition for ADC_CCR register ********************/
1592#define ADC_CCR_MULTI_Pos (0U)
1593#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1594#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1595#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1596#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1597#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1598#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1599#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1600#define ADC_CCR_DELAY_Pos (8U)
1601#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1602#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1603#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1604#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1605#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1606#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1607#define ADC_CCR_DDS_Pos (13U)
1608#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1609#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1610#define ADC_CCR_DMA_Pos (14U)
1611#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1612#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1613#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1614#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1615#define ADC_CCR_ADCPRE_Pos (16U)
1616#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1617#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1618#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1619#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1620#define ADC_CCR_VBATE_Pos (22U)
1621#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1622#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1623#define ADC_CCR_TSVREFE_Pos (23U)
1624#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1625#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1626
1627/******************* Bit definition for ADC_CDR register ********************/
1628#define ADC_CDR_DATA1_Pos (0U)
1629#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1630#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1631#define ADC_CDR_DATA2_Pos (16U)
1632#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1633#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1634
1635/* Legacy defines */
1636#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1637#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1638
1639/******************************************************************************/
1640/* */
1641/* Controller Area Network */
1642/* */
1643/******************************************************************************/
1645/******************* Bit definition for CAN_MCR register ********************/
1646#define CAN_MCR_INRQ_Pos (0U)
1647#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1648#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1649#define CAN_MCR_SLEEP_Pos (1U)
1650#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1651#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1652#define CAN_MCR_TXFP_Pos (2U)
1653#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1654#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1655#define CAN_MCR_RFLM_Pos (3U)
1656#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1657#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1658#define CAN_MCR_NART_Pos (4U)
1659#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1660#define CAN_MCR_NART CAN_MCR_NART_Msk
1661#define CAN_MCR_AWUM_Pos (5U)
1662#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1663#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1664#define CAN_MCR_ABOM_Pos (6U)
1665#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1666#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1667#define CAN_MCR_TTCM_Pos (7U)
1668#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1669#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1670#define CAN_MCR_RESET_Pos (15U)
1671#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1672#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1673#define CAN_MCR_DBF_Pos (16U)
1674#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1675#define CAN_MCR_DBF CAN_MCR_DBF_Msk
1676/******************* Bit definition for CAN_MSR register ********************/
1677#define CAN_MSR_INAK_Pos (0U)
1678#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1679#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1680#define CAN_MSR_SLAK_Pos (1U)
1681#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1682#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1683#define CAN_MSR_ERRI_Pos (2U)
1684#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1685#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1686#define CAN_MSR_WKUI_Pos (3U)
1687#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1688#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1689#define CAN_MSR_SLAKI_Pos (4U)
1690#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1691#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1692#define CAN_MSR_TXM_Pos (8U)
1693#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1694#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1695#define CAN_MSR_RXM_Pos (9U)
1696#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1697#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1698#define CAN_MSR_SAMP_Pos (10U)
1699#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1700#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1701#define CAN_MSR_RX_Pos (11U)
1702#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1703#define CAN_MSR_RX CAN_MSR_RX_Msk
1704
1705/******************* Bit definition for CAN_TSR register ********************/
1706#define CAN_TSR_RQCP0_Pos (0U)
1707#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1708#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1709#define CAN_TSR_TXOK0_Pos (1U)
1710#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1711#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1712#define CAN_TSR_ALST0_Pos (2U)
1713#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1714#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1715#define CAN_TSR_TERR0_Pos (3U)
1716#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1717#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1718#define CAN_TSR_ABRQ0_Pos (7U)
1719#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1720#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1721#define CAN_TSR_RQCP1_Pos (8U)
1722#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1723#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1724#define CAN_TSR_TXOK1_Pos (9U)
1725#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1726#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1727#define CAN_TSR_ALST1_Pos (10U)
1728#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1729#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1730#define CAN_TSR_TERR1_Pos (11U)
1731#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1732#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1733#define CAN_TSR_ABRQ1_Pos (15U)
1734#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1735#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1736#define CAN_TSR_RQCP2_Pos (16U)
1737#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1738#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1739#define CAN_TSR_TXOK2_Pos (17U)
1740#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1741#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1742#define CAN_TSR_ALST2_Pos (18U)
1743#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1744#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1745#define CAN_TSR_TERR2_Pos (19U)
1746#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1747#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1748#define CAN_TSR_ABRQ2_Pos (23U)
1749#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1750#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1751#define CAN_TSR_CODE_Pos (24U)
1752#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1753#define CAN_TSR_CODE CAN_TSR_CODE_Msk
1754
1755#define CAN_TSR_TME_Pos (26U)
1756#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1757#define CAN_TSR_TME CAN_TSR_TME_Msk
1758#define CAN_TSR_TME0_Pos (26U)
1759#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1760#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1761#define CAN_TSR_TME1_Pos (27U)
1762#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1763#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1764#define CAN_TSR_TME2_Pos (28U)
1765#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1766#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1767
1768#define CAN_TSR_LOW_Pos (29U)
1769#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1770#define CAN_TSR_LOW CAN_TSR_LOW_Msk
1771#define CAN_TSR_LOW0_Pos (29U)
1772#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1773#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1774#define CAN_TSR_LOW1_Pos (30U)
1775#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1776#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1777#define CAN_TSR_LOW2_Pos (31U)
1778#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1779#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1780
1781/******************* Bit definition for CAN_RF0R register *******************/
1782#define CAN_RF0R_FMP0_Pos (0U)
1783#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1784#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1785#define CAN_RF0R_FULL0_Pos (3U)
1786#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1787#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1788#define CAN_RF0R_FOVR0_Pos (4U)
1789#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1790#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1791#define CAN_RF0R_RFOM0_Pos (5U)
1792#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1793#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1794
1795/******************* Bit definition for CAN_RF1R register *******************/
1796#define CAN_RF1R_FMP1_Pos (0U)
1797#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1798#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1799#define CAN_RF1R_FULL1_Pos (3U)
1800#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1801#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1802#define CAN_RF1R_FOVR1_Pos (4U)
1803#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1804#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1805#define CAN_RF1R_RFOM1_Pos (5U)
1806#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1807#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1808
1809/******************** Bit definition for CAN_IER register *******************/
1810#define CAN_IER_TMEIE_Pos (0U)
1811#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1812#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1813#define CAN_IER_FMPIE0_Pos (1U)
1814#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1815#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1816#define CAN_IER_FFIE0_Pos (2U)
1817#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1818#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1819#define CAN_IER_FOVIE0_Pos (3U)
1820#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1821#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1822#define CAN_IER_FMPIE1_Pos (4U)
1823#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1824#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1825#define CAN_IER_FFIE1_Pos (5U)
1826#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1827#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1828#define CAN_IER_FOVIE1_Pos (6U)
1829#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1830#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1831#define CAN_IER_EWGIE_Pos (8U)
1832#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1833#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1834#define CAN_IER_EPVIE_Pos (9U)
1835#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1836#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1837#define CAN_IER_BOFIE_Pos (10U)
1838#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1839#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1840#define CAN_IER_LECIE_Pos (11U)
1841#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1842#define CAN_IER_LECIE CAN_IER_LECIE_Msk
1843#define CAN_IER_ERRIE_Pos (15U)
1844#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1845#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1846#define CAN_IER_WKUIE_Pos (16U)
1847#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1848#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1849#define CAN_IER_SLKIE_Pos (17U)
1850#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1851#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1852#define CAN_IER_EWGIE_Pos (8U)
1853
1854/******************** Bit definition for CAN_ESR register *******************/
1855#define CAN_ESR_EWGF_Pos (0U)
1856#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1857#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1858#define CAN_ESR_EPVF_Pos (1U)
1859#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1860#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1861#define CAN_ESR_BOFF_Pos (2U)
1862#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1863#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1864
1865#define CAN_ESR_LEC_Pos (4U)
1866#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
1867#define CAN_ESR_LEC CAN_ESR_LEC_Msk
1868#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
1869#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
1870#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
1871
1872#define CAN_ESR_TEC_Pos (16U)
1873#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
1874#define CAN_ESR_TEC CAN_ESR_TEC_Msk
1875#define CAN_ESR_REC_Pos (24U)
1876#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
1877#define CAN_ESR_REC CAN_ESR_REC_Msk
1878
1879/******************* Bit definition for CAN_BTR register ********************/
1880#define CAN_BTR_BRP_Pos (0U)
1881#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
1882#define CAN_BTR_BRP CAN_BTR_BRP_Msk
1883#define CAN_BTR_TS1_Pos (16U)
1884#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
1885#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
1886#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
1887#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
1888#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
1889#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
1890#define CAN_BTR_TS2_Pos (20U)
1891#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
1892#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
1893#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
1894#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
1895#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
1896#define CAN_BTR_SJW_Pos (24U)
1897#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
1898#define CAN_BTR_SJW CAN_BTR_SJW_Msk
1899#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
1900#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
1901#define CAN_BTR_LBKM_Pos (30U)
1902#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
1903#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
1904#define CAN_BTR_SILM_Pos (31U)
1905#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
1906#define CAN_BTR_SILM CAN_BTR_SILM_Msk
1907
1908
1910/****************** Bit definition for CAN_TI0R register ********************/
1911#define CAN_TI0R_TXRQ_Pos (0U)
1912#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
1913#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
1914#define CAN_TI0R_RTR_Pos (1U)
1915#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
1916#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
1917#define CAN_TI0R_IDE_Pos (2U)
1918#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
1919#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
1920#define CAN_TI0R_EXID_Pos (3U)
1921#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
1922#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
1923#define CAN_TI0R_STID_Pos (21U)
1924#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
1925#define CAN_TI0R_STID CAN_TI0R_STID_Msk
1926
1927/****************** Bit definition for CAN_TDT0R register *******************/
1928#define CAN_TDT0R_DLC_Pos (0U)
1929#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
1930#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
1931#define CAN_TDT0R_TGT_Pos (8U)
1932#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
1933#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
1934#define CAN_TDT0R_TIME_Pos (16U)
1935#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
1936#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
1937
1938/****************** Bit definition for CAN_TDL0R register *******************/
1939#define CAN_TDL0R_DATA0_Pos (0U)
1940#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
1941#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
1942#define CAN_TDL0R_DATA1_Pos (8U)
1943#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
1944#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
1945#define CAN_TDL0R_DATA2_Pos (16U)
1946#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
1947#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
1948#define CAN_TDL0R_DATA3_Pos (24U)
1949#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
1950#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
1951
1952/****************** Bit definition for CAN_TDH0R register *******************/
1953#define CAN_TDH0R_DATA4_Pos (0U)
1954#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
1955#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
1956#define CAN_TDH0R_DATA5_Pos (8U)
1957#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
1958#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
1959#define CAN_TDH0R_DATA6_Pos (16U)
1960#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
1961#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
1962#define CAN_TDH0R_DATA7_Pos (24U)
1963#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
1964#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
1965
1966/******************* Bit definition for CAN_TI1R register *******************/
1967#define CAN_TI1R_TXRQ_Pos (0U)
1968#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
1969#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
1970#define CAN_TI1R_RTR_Pos (1U)
1971#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
1972#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
1973#define CAN_TI1R_IDE_Pos (2U)
1974#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
1975#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
1976#define CAN_TI1R_EXID_Pos (3U)
1977#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
1978#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
1979#define CAN_TI1R_STID_Pos (21U)
1980#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
1981#define CAN_TI1R_STID CAN_TI1R_STID_Msk
1982
1983/******************* Bit definition for CAN_TDT1R register ******************/
1984#define CAN_TDT1R_DLC_Pos (0U)
1985#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
1986#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
1987#define CAN_TDT1R_TGT_Pos (8U)
1988#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
1989#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
1990#define CAN_TDT1R_TIME_Pos (16U)
1991#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
1992#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
1993
1994/******************* Bit definition for CAN_TDL1R register ******************/
1995#define CAN_TDL1R_DATA0_Pos (0U)
1996#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
1997#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
1998#define CAN_TDL1R_DATA1_Pos (8U)
1999#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2000#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2001#define CAN_TDL1R_DATA2_Pos (16U)
2002#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2003#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2004#define CAN_TDL1R_DATA3_Pos (24U)
2005#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2006#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2007
2008/******************* Bit definition for CAN_TDH1R register ******************/
2009#define CAN_TDH1R_DATA4_Pos (0U)
2010#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2011#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2012#define CAN_TDH1R_DATA5_Pos (8U)
2013#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2014#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2015#define CAN_TDH1R_DATA6_Pos (16U)
2016#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2017#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2018#define CAN_TDH1R_DATA7_Pos (24U)
2019#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2020#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2021
2022/******************* Bit definition for CAN_TI2R register *******************/
2023#define CAN_TI2R_TXRQ_Pos (0U)
2024#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2025#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2026#define CAN_TI2R_RTR_Pos (1U)
2027#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2028#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2029#define CAN_TI2R_IDE_Pos (2U)
2030#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2031#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2032#define CAN_TI2R_EXID_Pos (3U)
2033#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2034#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2035#define CAN_TI2R_STID_Pos (21U)
2036#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2037#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2038
2039/******************* Bit definition for CAN_TDT2R register ******************/
2040#define CAN_TDT2R_DLC_Pos (0U)
2041#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2042#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2043#define CAN_TDT2R_TGT_Pos (8U)
2044#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2045#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2046#define CAN_TDT2R_TIME_Pos (16U)
2047#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2048#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2049
2050/******************* Bit definition for CAN_TDL2R register ******************/
2051#define CAN_TDL2R_DATA0_Pos (0U)
2052#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2053#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2054#define CAN_TDL2R_DATA1_Pos (8U)
2055#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2056#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2057#define CAN_TDL2R_DATA2_Pos (16U)
2058#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2059#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2060#define CAN_TDL2R_DATA3_Pos (24U)
2061#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2062#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2063
2064/******************* Bit definition for CAN_TDH2R register ******************/
2065#define CAN_TDH2R_DATA4_Pos (0U)
2066#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2067#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2068#define CAN_TDH2R_DATA5_Pos (8U)
2069#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2070#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2071#define CAN_TDH2R_DATA6_Pos (16U)
2072#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2073#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2074#define CAN_TDH2R_DATA7_Pos (24U)
2075#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2076#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2077
2078/******************* Bit definition for CAN_RI0R register *******************/
2079#define CAN_RI0R_RTR_Pos (1U)
2080#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2081#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2082#define CAN_RI0R_IDE_Pos (2U)
2083#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2084#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2085#define CAN_RI0R_EXID_Pos (3U)
2086#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2087#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2088#define CAN_RI0R_STID_Pos (21U)
2089#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2090#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2091
2092/******************* Bit definition for CAN_RDT0R register ******************/
2093#define CAN_RDT0R_DLC_Pos (0U)
2094#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2095#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2096#define CAN_RDT0R_FMI_Pos (8U)
2097#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2098#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2099#define CAN_RDT0R_TIME_Pos (16U)
2100#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2101#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2102
2103/******************* Bit definition for CAN_RDL0R register ******************/
2104#define CAN_RDL0R_DATA0_Pos (0U)
2105#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2106#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2107#define CAN_RDL0R_DATA1_Pos (8U)
2108#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2109#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2110#define CAN_RDL0R_DATA2_Pos (16U)
2111#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2112#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2113#define CAN_RDL0R_DATA3_Pos (24U)
2114#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2115#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2116
2117/******************* Bit definition for CAN_RDH0R register ******************/
2118#define CAN_RDH0R_DATA4_Pos (0U)
2119#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2120#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2121#define CAN_RDH0R_DATA5_Pos (8U)
2122#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2123#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2124#define CAN_RDH0R_DATA6_Pos (16U)
2125#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2126#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2127#define CAN_RDH0R_DATA7_Pos (24U)
2128#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2129#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2130
2131/******************* Bit definition for CAN_RI1R register *******************/
2132#define CAN_RI1R_RTR_Pos (1U)
2133#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2134#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2135#define CAN_RI1R_IDE_Pos (2U)
2136#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2137#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2138#define CAN_RI1R_EXID_Pos (3U)
2139#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2140#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2141#define CAN_RI1R_STID_Pos (21U)
2142#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2143#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2144
2145/******************* Bit definition for CAN_RDT1R register ******************/
2146#define CAN_RDT1R_DLC_Pos (0U)
2147#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2148#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2149#define CAN_RDT1R_FMI_Pos (8U)
2150#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2151#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2152#define CAN_RDT1R_TIME_Pos (16U)
2153#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2154#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2155
2156/******************* Bit definition for CAN_RDL1R register ******************/
2157#define CAN_RDL1R_DATA0_Pos (0U)
2158#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2159#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2160#define CAN_RDL1R_DATA1_Pos (8U)
2161#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2162#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2163#define CAN_RDL1R_DATA2_Pos (16U)
2164#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2165#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2166#define CAN_RDL1R_DATA3_Pos (24U)
2167#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2168#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2169
2170/******************* Bit definition for CAN_RDH1R register ******************/
2171#define CAN_RDH1R_DATA4_Pos (0U)
2172#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2173#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2174#define CAN_RDH1R_DATA5_Pos (8U)
2175#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2176#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2177#define CAN_RDH1R_DATA6_Pos (16U)
2178#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2179#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2180#define CAN_RDH1R_DATA7_Pos (24U)
2181#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2182#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2183
2185/******************* Bit definition for CAN_FMR register ********************/
2186#define CAN_FMR_FINIT_Pos (0U)
2187#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2188#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2189#define CAN_FMR_CAN2SB_Pos (8U)
2190#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2191#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2192
2193/******************* Bit definition for CAN_FM1R register *******************/
2194#define CAN_FM1R_FBM_Pos (0U)
2195#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2196#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2197#define CAN_FM1R_FBM0_Pos (0U)
2198#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2199#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2200#define CAN_FM1R_FBM1_Pos (1U)
2201#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2202#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2203#define CAN_FM1R_FBM2_Pos (2U)
2204#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2205#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2206#define CAN_FM1R_FBM3_Pos (3U)
2207#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2208#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2209#define CAN_FM1R_FBM4_Pos (4U)
2210#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2211#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2212#define CAN_FM1R_FBM5_Pos (5U)
2213#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2214#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2215#define CAN_FM1R_FBM6_Pos (6U)
2216#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2217#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2218#define CAN_FM1R_FBM7_Pos (7U)
2219#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2220#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2221#define CAN_FM1R_FBM8_Pos (8U)
2222#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2223#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2224#define CAN_FM1R_FBM9_Pos (9U)
2225#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2226#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2227#define CAN_FM1R_FBM10_Pos (10U)
2228#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2229#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2230#define CAN_FM1R_FBM11_Pos (11U)
2231#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2232#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2233#define CAN_FM1R_FBM12_Pos (12U)
2234#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2235#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2236#define CAN_FM1R_FBM13_Pos (13U)
2237#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2238#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2239#define CAN_FM1R_FBM14_Pos (14U)
2240#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2241#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2242#define CAN_FM1R_FBM15_Pos (15U)
2243#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2244#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2245#define CAN_FM1R_FBM16_Pos (16U)
2246#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2247#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2248#define CAN_FM1R_FBM17_Pos (17U)
2249#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2250#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2251#define CAN_FM1R_FBM18_Pos (18U)
2252#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2253#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2254#define CAN_FM1R_FBM19_Pos (19U)
2255#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2256#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2257#define CAN_FM1R_FBM20_Pos (20U)
2258#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2259#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2260#define CAN_FM1R_FBM21_Pos (21U)
2261#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2262#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2263#define CAN_FM1R_FBM22_Pos (22U)
2264#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2265#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2266#define CAN_FM1R_FBM23_Pos (23U)
2267#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2268#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2269#define CAN_FM1R_FBM24_Pos (24U)
2270#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2271#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2272#define CAN_FM1R_FBM25_Pos (25U)
2273#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2274#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2275#define CAN_FM1R_FBM26_Pos (26U)
2276#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2277#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2278#define CAN_FM1R_FBM27_Pos (27U)
2279#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2280#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2281
2282/******************* Bit definition for CAN_FS1R register *******************/
2283#define CAN_FS1R_FSC_Pos (0U)
2284#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2285#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2286#define CAN_FS1R_FSC0_Pos (0U)
2287#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2288#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2289#define CAN_FS1R_FSC1_Pos (1U)
2290#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2291#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2292#define CAN_FS1R_FSC2_Pos (2U)
2293#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2294#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2295#define CAN_FS1R_FSC3_Pos (3U)
2296#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2297#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2298#define CAN_FS1R_FSC4_Pos (4U)
2299#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2300#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2301#define CAN_FS1R_FSC5_Pos (5U)
2302#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2303#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2304#define CAN_FS1R_FSC6_Pos (6U)
2305#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2306#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2307#define CAN_FS1R_FSC7_Pos (7U)
2308#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2309#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2310#define CAN_FS1R_FSC8_Pos (8U)
2311#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2312#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2313#define CAN_FS1R_FSC9_Pos (9U)
2314#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2315#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2316#define CAN_FS1R_FSC10_Pos (10U)
2317#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2318#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2319#define CAN_FS1R_FSC11_Pos (11U)
2320#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2321#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2322#define CAN_FS1R_FSC12_Pos (12U)
2323#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2324#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2325#define CAN_FS1R_FSC13_Pos (13U)
2326#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2327#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2328#define CAN_FS1R_FSC14_Pos (14U)
2329#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2330#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2331#define CAN_FS1R_FSC15_Pos (15U)
2332#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2333#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2334#define CAN_FS1R_FSC16_Pos (16U)
2335#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2336#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2337#define CAN_FS1R_FSC17_Pos (17U)
2338#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2339#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2340#define CAN_FS1R_FSC18_Pos (18U)
2341#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2342#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2343#define CAN_FS1R_FSC19_Pos (19U)
2344#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2345#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2346#define CAN_FS1R_FSC20_Pos (20U)
2347#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2348#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2349#define CAN_FS1R_FSC21_Pos (21U)
2350#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2351#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2352#define CAN_FS1R_FSC22_Pos (22U)
2353#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2354#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2355#define CAN_FS1R_FSC23_Pos (23U)
2356#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2357#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2358#define CAN_FS1R_FSC24_Pos (24U)
2359#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2360#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2361#define CAN_FS1R_FSC25_Pos (25U)
2362#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2363#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2364#define CAN_FS1R_FSC26_Pos (26U)
2365#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2366#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2367#define CAN_FS1R_FSC27_Pos (27U)
2368#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2369#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2370
2371/****************** Bit definition for CAN_FFA1R register *******************/
2372#define CAN_FFA1R_FFA_Pos (0U)
2373#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2374#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2375#define CAN_FFA1R_FFA0_Pos (0U)
2376#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2377#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2378#define CAN_FFA1R_FFA1_Pos (1U)
2379#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2380#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2381#define CAN_FFA1R_FFA2_Pos (2U)
2382#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2383#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2384#define CAN_FFA1R_FFA3_Pos (3U)
2385#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2386#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2387#define CAN_FFA1R_FFA4_Pos (4U)
2388#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2389#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2390#define CAN_FFA1R_FFA5_Pos (5U)
2391#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2392#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2393#define CAN_FFA1R_FFA6_Pos (6U)
2394#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2395#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2396#define CAN_FFA1R_FFA7_Pos (7U)
2397#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2398#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2399#define CAN_FFA1R_FFA8_Pos (8U)
2400#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2401#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2402#define CAN_FFA1R_FFA9_Pos (9U)
2403#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2404#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2405#define CAN_FFA1R_FFA10_Pos (10U)
2406#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2407#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2408#define CAN_FFA1R_FFA11_Pos (11U)
2409#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2410#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2411#define CAN_FFA1R_FFA12_Pos (12U)
2412#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2413#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2414#define CAN_FFA1R_FFA13_Pos (13U)
2415#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2416#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2417#define CAN_FFA1R_FFA14_Pos (14U)
2418#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2419#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2420#define CAN_FFA1R_FFA15_Pos (15U)
2421#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2422#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2423#define CAN_FFA1R_FFA16_Pos (16U)
2424#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2425#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2426#define CAN_FFA1R_FFA17_Pos (17U)
2427#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2428#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2429#define CAN_FFA1R_FFA18_Pos (18U)
2430#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2431#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2432#define CAN_FFA1R_FFA19_Pos (19U)
2433#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2434#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2435#define CAN_FFA1R_FFA20_Pos (20U)
2436#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2437#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2438#define CAN_FFA1R_FFA21_Pos (21U)
2439#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2440#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2441#define CAN_FFA1R_FFA22_Pos (22U)
2442#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2443#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2444#define CAN_FFA1R_FFA23_Pos (23U)
2445#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2446#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2447#define CAN_FFA1R_FFA24_Pos (24U)
2448#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2449#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2450#define CAN_FFA1R_FFA25_Pos (25U)
2451#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2452#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2453#define CAN_FFA1R_FFA26_Pos (26U)
2454#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2455#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2456#define CAN_FFA1R_FFA27_Pos (27U)
2457#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2458#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2459
2460/******************* Bit definition for CAN_FA1R register *******************/
2461#define CAN_FA1R_FACT_Pos (0U)
2462#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2463#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2464#define CAN_FA1R_FACT0_Pos (0U)
2465#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2466#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2467#define CAN_FA1R_FACT1_Pos (1U)
2468#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2469#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2470#define CAN_FA1R_FACT2_Pos (2U)
2471#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2472#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2473#define CAN_FA1R_FACT3_Pos (3U)
2474#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2475#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2476#define CAN_FA1R_FACT4_Pos (4U)
2477#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2478#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2479#define CAN_FA1R_FACT5_Pos (5U)
2480#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2481#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2482#define CAN_FA1R_FACT6_Pos (6U)
2483#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2484#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2485#define CAN_FA1R_FACT7_Pos (7U)
2486#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2487#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2488#define CAN_FA1R_FACT8_Pos (8U)
2489#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2490#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2491#define CAN_FA1R_FACT9_Pos (9U)
2492#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2493#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2494#define CAN_FA1R_FACT10_Pos (10U)
2495#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2496#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2497#define CAN_FA1R_FACT11_Pos (11U)
2498#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2499#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2500#define CAN_FA1R_FACT12_Pos (12U)
2501#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2502#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2503#define CAN_FA1R_FACT13_Pos (13U)
2504#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2505#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2506#define CAN_FA1R_FACT14_Pos (14U)
2507#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2508#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2509#define CAN_FA1R_FACT15_Pos (15U)
2510#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2511#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2512#define CAN_FA1R_FACT16_Pos (16U)
2513#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2514#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2515#define CAN_FA1R_FACT17_Pos (17U)
2516#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2517#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2518#define CAN_FA1R_FACT18_Pos (18U)
2519#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2520#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2521#define CAN_FA1R_FACT19_Pos (19U)
2522#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2523#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2524#define CAN_FA1R_FACT20_Pos (20U)
2525#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2526#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2527#define CAN_FA1R_FACT21_Pos (21U)
2528#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2529#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2530#define CAN_FA1R_FACT22_Pos (22U)
2531#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2532#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2533#define CAN_FA1R_FACT23_Pos (23U)
2534#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2535#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2536#define CAN_FA1R_FACT24_Pos (24U)
2537#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2538#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2539#define CAN_FA1R_FACT25_Pos (25U)
2540#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2541#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2542#define CAN_FA1R_FACT26_Pos (26U)
2543#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2544#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2545#define CAN_FA1R_FACT27_Pos (27U)
2546#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2547#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2548
2549
2550/******************* Bit definition for CAN_F0R1 register *******************/
2551#define CAN_F0R1_FB0_Pos (0U)
2552#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2553#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2554#define CAN_F0R1_FB1_Pos (1U)
2555#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2556#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2557#define CAN_F0R1_FB2_Pos (2U)
2558#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2559#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2560#define CAN_F0R1_FB3_Pos (3U)
2561#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2562#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2563#define CAN_F0R1_FB4_Pos (4U)
2564#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2565#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2566#define CAN_F0R1_FB5_Pos (5U)
2567#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2568#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2569#define CAN_F0R1_FB6_Pos (6U)
2570#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2571#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2572#define CAN_F0R1_FB7_Pos (7U)
2573#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2574#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2575#define CAN_F0R1_FB8_Pos (8U)
2576#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2577#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2578#define CAN_F0R1_FB9_Pos (9U)
2579#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2580#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2581#define CAN_F0R1_FB10_Pos (10U)
2582#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2583#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2584#define CAN_F0R1_FB11_Pos (11U)
2585#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2586#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2587#define CAN_F0R1_FB12_Pos (12U)
2588#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2589#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2590#define CAN_F0R1_FB13_Pos (13U)
2591#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2592#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2593#define CAN_F0R1_FB14_Pos (14U)
2594#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2595#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2596#define CAN_F0R1_FB15_Pos (15U)
2597#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2598#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2599#define CAN_F0R1_FB16_Pos (16U)
2600#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2601#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2602#define CAN_F0R1_FB17_Pos (17U)
2603#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2604#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2605#define CAN_F0R1_FB18_Pos (18U)
2606#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2607#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2608#define CAN_F0R1_FB19_Pos (19U)
2609#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2610#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2611#define CAN_F0R1_FB20_Pos (20U)
2612#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2613#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2614#define CAN_F0R1_FB21_Pos (21U)
2615#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2616#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2617#define CAN_F0R1_FB22_Pos (22U)
2618#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2619#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2620#define CAN_F0R1_FB23_Pos (23U)
2621#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2622#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2623#define CAN_F0R1_FB24_Pos (24U)
2624#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2625#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2626#define CAN_F0R1_FB25_Pos (25U)
2627#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2628#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2629#define CAN_F0R1_FB26_Pos (26U)
2630#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2631#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2632#define CAN_F0R1_FB27_Pos (27U)
2633#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2634#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2635#define CAN_F0R1_FB28_Pos (28U)
2636#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2637#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2638#define CAN_F0R1_FB29_Pos (29U)
2639#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2640#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2641#define CAN_F0R1_FB30_Pos (30U)
2642#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2643#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2644#define CAN_F0R1_FB31_Pos (31U)
2645#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2646#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2647
2648/******************* Bit definition for CAN_F1R1 register *******************/
2649#define CAN_F1R1_FB0_Pos (0U)
2650#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2651#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2652#define CAN_F1R1_FB1_Pos (1U)
2653#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2654#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2655#define CAN_F1R1_FB2_Pos (2U)
2656#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2657#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2658#define CAN_F1R1_FB3_Pos (3U)
2659#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2660#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2661#define CAN_F1R1_FB4_Pos (4U)
2662#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2663#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2664#define CAN_F1R1_FB5_Pos (5U)
2665#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2666#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2667#define CAN_F1R1_FB6_Pos (6U)
2668#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2669#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2670#define CAN_F1R1_FB7_Pos (7U)
2671#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2672#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2673#define CAN_F1R1_FB8_Pos (8U)
2674#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2675#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2676#define CAN_F1R1_FB9_Pos (9U)
2677#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2678#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2679#define CAN_F1R1_FB10_Pos (10U)
2680#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2681#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2682#define CAN_F1R1_FB11_Pos (11U)
2683#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2684#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2685#define CAN_F1R1_FB12_Pos (12U)
2686#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2687#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2688#define CAN_F1R1_FB13_Pos (13U)
2689#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2690#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2691#define CAN_F1R1_FB14_Pos (14U)
2692#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2693#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2694#define CAN_F1R1_FB15_Pos (15U)
2695#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2696#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2697#define CAN_F1R1_FB16_Pos (16U)
2698#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2699#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2700#define CAN_F1R1_FB17_Pos (17U)
2701#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2702#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2703#define CAN_F1R1_FB18_Pos (18U)
2704#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2705#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2706#define CAN_F1R1_FB19_Pos (19U)
2707#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2708#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2709#define CAN_F1R1_FB20_Pos (20U)
2710#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2711#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2712#define CAN_F1R1_FB21_Pos (21U)
2713#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2714#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2715#define CAN_F1R1_FB22_Pos (22U)
2716#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2717#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2718#define CAN_F1R1_FB23_Pos (23U)
2719#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2720#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2721#define CAN_F1R1_FB24_Pos (24U)
2722#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2723#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2724#define CAN_F1R1_FB25_Pos (25U)
2725#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2726#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2727#define CAN_F1R1_FB26_Pos (26U)
2728#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2729#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2730#define CAN_F1R1_FB27_Pos (27U)
2731#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2732#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2733#define CAN_F1R1_FB28_Pos (28U)
2734#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2735#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2736#define CAN_F1R1_FB29_Pos (29U)
2737#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2738#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2739#define CAN_F1R1_FB30_Pos (30U)
2740#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2741#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2742#define CAN_F1R1_FB31_Pos (31U)
2743#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2744#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2745
2746/******************* Bit definition for CAN_F2R1 register *******************/
2747#define CAN_F2R1_FB0_Pos (0U)
2748#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2749#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2750#define CAN_F2R1_FB1_Pos (1U)
2751#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2752#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2753#define CAN_F2R1_FB2_Pos (2U)
2754#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2755#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2756#define CAN_F2R1_FB3_Pos (3U)
2757#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2758#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2759#define CAN_F2R1_FB4_Pos (4U)
2760#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2761#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2762#define CAN_F2R1_FB5_Pos (5U)
2763#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2764#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2765#define CAN_F2R1_FB6_Pos (6U)
2766#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2767#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2768#define CAN_F2R1_FB7_Pos (7U)
2769#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2770#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2771#define CAN_F2R1_FB8_Pos (8U)
2772#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2773#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2774#define CAN_F2R1_FB9_Pos (9U)
2775#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2776#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2777#define CAN_F2R1_FB10_Pos (10U)
2778#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2779#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2780#define CAN_F2R1_FB11_Pos (11U)
2781#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2782#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2783#define CAN_F2R1_FB12_Pos (12U)
2784#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2785#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2786#define CAN_F2R1_FB13_Pos (13U)
2787#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2788#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2789#define CAN_F2R1_FB14_Pos (14U)
2790#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2791#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2792#define CAN_F2R1_FB15_Pos (15U)
2793#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2794#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2795#define CAN_F2R1_FB16_Pos (16U)
2796#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2797#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2798#define CAN_F2R1_FB17_Pos (17U)
2799#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2800#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2801#define CAN_F2R1_FB18_Pos (18U)
2802#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2803#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2804#define CAN_F2R1_FB19_Pos (19U)
2805#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2806#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2807#define CAN_F2R1_FB20_Pos (20U)
2808#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2809#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2810#define CAN_F2R1_FB21_Pos (21U)
2811#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2812#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2813#define CAN_F2R1_FB22_Pos (22U)
2814#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2815#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2816#define CAN_F2R1_FB23_Pos (23U)
2817#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2818#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2819#define CAN_F2R1_FB24_Pos (24U)
2820#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2821#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2822#define CAN_F2R1_FB25_Pos (25U)
2823#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2824#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2825#define CAN_F2R1_FB26_Pos (26U)
2826#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2827#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2828#define CAN_F2R1_FB27_Pos (27U)
2829#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2830#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2831#define CAN_F2R1_FB28_Pos (28U)
2832#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2833#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2834#define CAN_F2R1_FB29_Pos (29U)
2835#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2836#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2837#define CAN_F2R1_FB30_Pos (30U)
2838#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2839#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2840#define CAN_F2R1_FB31_Pos (31U)
2841#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2842#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2843
2844/******************* Bit definition for CAN_F3R1 register *******************/
2845#define CAN_F3R1_FB0_Pos (0U)
2846#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2847#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2848#define CAN_F3R1_FB1_Pos (1U)
2849#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2850#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2851#define CAN_F3R1_FB2_Pos (2U)
2852#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2853#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2854#define CAN_F3R1_FB3_Pos (3U)
2855#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2856#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2857#define CAN_F3R1_FB4_Pos (4U)
2858#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2859#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2860#define CAN_F3R1_FB5_Pos (5U)
2861#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2862#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2863#define CAN_F3R1_FB6_Pos (6U)
2864#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2865#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2866#define CAN_F3R1_FB7_Pos (7U)
2867#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
2868#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
2869#define CAN_F3R1_FB8_Pos (8U)
2870#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
2871#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
2872#define CAN_F3R1_FB9_Pos (9U)
2873#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
2874#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
2875#define CAN_F3R1_FB10_Pos (10U)
2876#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
2877#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
2878#define CAN_F3R1_FB11_Pos (11U)
2879#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
2880#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
2881#define CAN_F3R1_FB12_Pos (12U)
2882#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
2883#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
2884#define CAN_F3R1_FB13_Pos (13U)
2885#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
2886#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
2887#define CAN_F3R1_FB14_Pos (14U)
2888#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
2889#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
2890#define CAN_F3R1_FB15_Pos (15U)
2891#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
2892#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
2893#define CAN_F3R1_FB16_Pos (16U)
2894#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
2895#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
2896#define CAN_F3R1_FB17_Pos (17U)
2897#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
2898#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
2899#define CAN_F3R1_FB18_Pos (18U)
2900#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
2901#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
2902#define CAN_F3R1_FB19_Pos (19U)
2903#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
2904#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
2905#define CAN_F3R1_FB20_Pos (20U)
2906#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
2907#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
2908#define CAN_F3R1_FB21_Pos (21U)
2909#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
2910#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
2911#define CAN_F3R1_FB22_Pos (22U)
2912#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
2913#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
2914#define CAN_F3R1_FB23_Pos (23U)
2915#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
2916#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
2917#define CAN_F3R1_FB24_Pos (24U)
2918#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
2919#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
2920#define CAN_F3R1_FB25_Pos (25U)
2921#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
2922#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
2923#define CAN_F3R1_FB26_Pos (26U)
2924#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
2925#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
2926#define CAN_F3R1_FB27_Pos (27U)
2927#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
2928#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
2929#define CAN_F3R1_FB28_Pos (28U)
2930#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
2931#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
2932#define CAN_F3R1_FB29_Pos (29U)
2933#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
2934#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
2935#define CAN_F3R1_FB30_Pos (30U)
2936#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
2937#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
2938#define CAN_F3R1_FB31_Pos (31U)
2939#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
2940#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
2941
2942/******************* Bit definition for CAN_F4R1 register *******************/
2943#define CAN_F4R1_FB0_Pos (0U)
2944#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
2945#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
2946#define CAN_F4R1_FB1_Pos (1U)
2947#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
2948#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
2949#define CAN_F4R1_FB2_Pos (2U)
2950#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
2951#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
2952#define CAN_F4R1_FB3_Pos (3U)
2953#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
2954#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
2955#define CAN_F4R1_FB4_Pos (4U)
2956#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
2957#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
2958#define CAN_F4R1_FB5_Pos (5U)
2959#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
2960#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
2961#define CAN_F4R1_FB6_Pos (6U)
2962#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
2963#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
2964#define CAN_F4R1_FB7_Pos (7U)
2965#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
2966#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
2967#define CAN_F4R1_FB8_Pos (8U)
2968#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
2969#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
2970#define CAN_F4R1_FB9_Pos (9U)
2971#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
2972#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
2973#define CAN_F4R1_FB10_Pos (10U)
2974#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
2975#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
2976#define CAN_F4R1_FB11_Pos (11U)
2977#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
2978#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
2979#define CAN_F4R1_FB12_Pos (12U)
2980#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
2981#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
2982#define CAN_F4R1_FB13_Pos (13U)
2983#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
2984#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
2985#define CAN_F4R1_FB14_Pos (14U)
2986#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
2987#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
2988#define CAN_F4R1_FB15_Pos (15U)
2989#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
2990#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
2991#define CAN_F4R1_FB16_Pos (16U)
2992#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
2993#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
2994#define CAN_F4R1_FB17_Pos (17U)
2995#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
2996#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
2997#define CAN_F4R1_FB18_Pos (18U)
2998#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
2999#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3000#define CAN_F4R1_FB19_Pos (19U)
3001#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3002#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3003#define CAN_F4R1_FB20_Pos (20U)
3004#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3005#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3006#define CAN_F4R1_FB21_Pos (21U)
3007#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3008#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3009#define CAN_F4R1_FB22_Pos (22U)
3010#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3011#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3012#define CAN_F4R1_FB23_Pos (23U)
3013#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3014#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3015#define CAN_F4R1_FB24_Pos (24U)
3016#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3017#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3018#define CAN_F4R1_FB25_Pos (25U)
3019#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3020#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3021#define CAN_F4R1_FB26_Pos (26U)
3022#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3023#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3024#define CAN_F4R1_FB27_Pos (27U)
3025#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3026#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3027#define CAN_F4R1_FB28_Pos (28U)
3028#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3029#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3030#define CAN_F4R1_FB29_Pos (29U)
3031#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3032#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3033#define CAN_F4R1_FB30_Pos (30U)
3034#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3035#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3036#define CAN_F4R1_FB31_Pos (31U)
3037#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3038#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3039
3040/******************* Bit definition for CAN_F5R1 register *******************/
3041#define CAN_F5R1_FB0_Pos (0U)
3042#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3043#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3044#define CAN_F5R1_FB1_Pos (1U)
3045#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3046#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3047#define CAN_F5R1_FB2_Pos (2U)
3048#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3049#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3050#define CAN_F5R1_FB3_Pos (3U)
3051#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3052#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3053#define CAN_F5R1_FB4_Pos (4U)
3054#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3055#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3056#define CAN_F5R1_FB5_Pos (5U)
3057#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3058#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3059#define CAN_F5R1_FB6_Pos (6U)
3060#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3061#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3062#define CAN_F5R1_FB7_Pos (7U)
3063#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3064#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3065#define CAN_F5R1_FB8_Pos (8U)
3066#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3067#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3068#define CAN_F5R1_FB9_Pos (9U)
3069#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3070#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3071#define CAN_F5R1_FB10_Pos (10U)
3072#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3073#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3074#define CAN_F5R1_FB11_Pos (11U)
3075#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3076#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3077#define CAN_F5R1_FB12_Pos (12U)
3078#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3079#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3080#define CAN_F5R1_FB13_Pos (13U)
3081#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3082#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3083#define CAN_F5R1_FB14_Pos (14U)
3084#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3085#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3086#define CAN_F5R1_FB15_Pos (15U)
3087#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3088#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3089#define CAN_F5R1_FB16_Pos (16U)
3090#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3091#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3092#define CAN_F5R1_FB17_Pos (17U)
3093#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3094#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3095#define CAN_F5R1_FB18_Pos (18U)
3096#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3097#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3098#define CAN_F5R1_FB19_Pos (19U)
3099#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3100#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3101#define CAN_F5R1_FB20_Pos (20U)
3102#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3103#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3104#define CAN_F5R1_FB21_Pos (21U)
3105#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3106#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3107#define CAN_F5R1_FB22_Pos (22U)
3108#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3109#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3110#define CAN_F5R1_FB23_Pos (23U)
3111#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3112#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3113#define CAN_F5R1_FB24_Pos (24U)
3114#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3115#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3116#define CAN_F5R1_FB25_Pos (25U)
3117#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3118#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3119#define CAN_F5R1_FB26_Pos (26U)
3120#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3121#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3122#define CAN_F5R1_FB27_Pos (27U)
3123#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3124#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3125#define CAN_F5R1_FB28_Pos (28U)
3126#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3127#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3128#define CAN_F5R1_FB29_Pos (29U)
3129#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3130#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3131#define CAN_F5R1_FB30_Pos (30U)
3132#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3133#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3134#define CAN_F5R1_FB31_Pos (31U)
3135#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3136#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3137
3138/******************* Bit definition for CAN_F6R1 register *******************/
3139#define CAN_F6R1_FB0_Pos (0U)
3140#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3141#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3142#define CAN_F6R1_FB1_Pos (1U)
3143#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3144#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3145#define CAN_F6R1_FB2_Pos (2U)
3146#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3147#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3148#define CAN_F6R1_FB3_Pos (3U)
3149#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3150#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3151#define CAN_F6R1_FB4_Pos (4U)
3152#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3153#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3154#define CAN_F6R1_FB5_Pos (5U)
3155#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3156#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3157#define CAN_F6R1_FB6_Pos (6U)
3158#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3159#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3160#define CAN_F6R1_FB7_Pos (7U)
3161#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3162#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3163#define CAN_F6R1_FB8_Pos (8U)
3164#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3165#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3166#define CAN_F6R1_FB9_Pos (9U)
3167#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3168#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3169#define CAN_F6R1_FB10_Pos (10U)
3170#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3171#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3172#define CAN_F6R1_FB11_Pos (11U)
3173#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3174#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3175#define CAN_F6R1_FB12_Pos (12U)
3176#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3177#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3178#define CAN_F6R1_FB13_Pos (13U)
3179#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3180#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3181#define CAN_F6R1_FB14_Pos (14U)
3182#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3183#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3184#define CAN_F6R1_FB15_Pos (15U)
3185#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3186#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3187#define CAN_F6R1_FB16_Pos (16U)
3188#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3189#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3190#define CAN_F6R1_FB17_Pos (17U)
3191#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3192#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3193#define CAN_F6R1_FB18_Pos (18U)
3194#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3195#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3196#define CAN_F6R1_FB19_Pos (19U)
3197#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3198#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3199#define CAN_F6R1_FB20_Pos (20U)
3200#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3201#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3202#define CAN_F6R1_FB21_Pos (21U)
3203#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3204#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3205#define CAN_F6R1_FB22_Pos (22U)
3206#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3207#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3208#define CAN_F6R1_FB23_Pos (23U)
3209#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3210#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3211#define CAN_F6R1_FB24_Pos (24U)
3212#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3213#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3214#define CAN_F6R1_FB25_Pos (25U)
3215#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3216#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3217#define CAN_F6R1_FB26_Pos (26U)
3218#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3219#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3220#define CAN_F6R1_FB27_Pos (27U)
3221#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3222#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3223#define CAN_F6R1_FB28_Pos (28U)
3224#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3225#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3226#define CAN_F6R1_FB29_Pos (29U)
3227#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3228#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3229#define CAN_F6R1_FB30_Pos (30U)
3230#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3231#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3232#define CAN_F6R1_FB31_Pos (31U)
3233#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3234#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3235
3236/******************* Bit definition for CAN_F7R1 register *******************/
3237#define CAN_F7R1_FB0_Pos (0U)
3238#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3239#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3240#define CAN_F7R1_FB1_Pos (1U)
3241#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3242#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3243#define CAN_F7R1_FB2_Pos (2U)
3244#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3245#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3246#define CAN_F7R1_FB3_Pos (3U)
3247#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3248#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3249#define CAN_F7R1_FB4_Pos (4U)
3250#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3251#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3252#define CAN_F7R1_FB5_Pos (5U)
3253#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3254#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3255#define CAN_F7R1_FB6_Pos (6U)
3256#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3257#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3258#define CAN_F7R1_FB7_Pos (7U)
3259#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3260#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3261#define CAN_F7R1_FB8_Pos (8U)
3262#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3263#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3264#define CAN_F7R1_FB9_Pos (9U)
3265#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3266#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3267#define CAN_F7R1_FB10_Pos (10U)
3268#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3269#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3270#define CAN_F7R1_FB11_Pos (11U)
3271#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3272#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3273#define CAN_F7R1_FB12_Pos (12U)
3274#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3275#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3276#define CAN_F7R1_FB13_Pos (13U)
3277#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3278#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3279#define CAN_F7R1_FB14_Pos (14U)
3280#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3281#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3282#define CAN_F7R1_FB15_Pos (15U)
3283#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3284#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3285#define CAN_F7R1_FB16_Pos (16U)
3286#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3287#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3288#define CAN_F7R1_FB17_Pos (17U)
3289#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3290#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3291#define CAN_F7R1_FB18_Pos (18U)
3292#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3293#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3294#define CAN_F7R1_FB19_Pos (19U)
3295#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3296#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3297#define CAN_F7R1_FB20_Pos (20U)
3298#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3299#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3300#define CAN_F7R1_FB21_Pos (21U)
3301#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3302#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3303#define CAN_F7R1_FB22_Pos (22U)
3304#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3305#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3306#define CAN_F7R1_FB23_Pos (23U)
3307#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3308#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3309#define CAN_F7R1_FB24_Pos (24U)
3310#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3311#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3312#define CAN_F7R1_FB25_Pos (25U)
3313#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3314#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3315#define CAN_F7R1_FB26_Pos (26U)
3316#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3317#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3318#define CAN_F7R1_FB27_Pos (27U)
3319#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3320#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3321#define CAN_F7R1_FB28_Pos (28U)
3322#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3323#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3324#define CAN_F7R1_FB29_Pos (29U)
3325#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3326#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3327#define CAN_F7R1_FB30_Pos (30U)
3328#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3329#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3330#define CAN_F7R1_FB31_Pos (31U)
3331#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3332#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3333
3334/******************* Bit definition for CAN_F8R1 register *******************/
3335#define CAN_F8R1_FB0_Pos (0U)
3336#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3337#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3338#define CAN_F8R1_FB1_Pos (1U)
3339#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3340#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3341#define CAN_F8R1_FB2_Pos (2U)
3342#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3343#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3344#define CAN_F8R1_FB3_Pos (3U)
3345#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3346#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3347#define CAN_F8R1_FB4_Pos (4U)
3348#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3349#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3350#define CAN_F8R1_FB5_Pos (5U)
3351#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3352#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3353#define CAN_F8R1_FB6_Pos (6U)
3354#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3355#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3356#define CAN_F8R1_FB7_Pos (7U)
3357#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3358#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3359#define CAN_F8R1_FB8_Pos (8U)
3360#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3361#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3362#define CAN_F8R1_FB9_Pos (9U)
3363#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3364#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3365#define CAN_F8R1_FB10_Pos (10U)
3366#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3367#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3368#define CAN_F8R1_FB11_Pos (11U)
3369#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3370#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3371#define CAN_F8R1_FB12_Pos (12U)
3372#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3373#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3374#define CAN_F8R1_FB13_Pos (13U)
3375#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3376#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3377#define CAN_F8R1_FB14_Pos (14U)
3378#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3379#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3380#define CAN_F8R1_FB15_Pos (15U)
3381#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3382#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3383#define CAN_F8R1_FB16_Pos (16U)
3384#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3385#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3386#define CAN_F8R1_FB17_Pos (17U)
3387#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3388#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3389#define CAN_F8R1_FB18_Pos (18U)
3390#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3391#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3392#define CAN_F8R1_FB19_Pos (19U)
3393#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3394#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3395#define CAN_F8R1_FB20_Pos (20U)
3396#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3397#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3398#define CAN_F8R1_FB21_Pos (21U)
3399#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3400#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3401#define CAN_F8R1_FB22_Pos (22U)
3402#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3403#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3404#define CAN_F8R1_FB23_Pos (23U)
3405#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3406#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3407#define CAN_F8R1_FB24_Pos (24U)
3408#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3409#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3410#define CAN_F8R1_FB25_Pos (25U)
3411#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3412#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3413#define CAN_F8R1_FB26_Pos (26U)
3414#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3415#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3416#define CAN_F8R1_FB27_Pos (27U)
3417#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3418#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3419#define CAN_F8R1_FB28_Pos (28U)
3420#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3421#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3422#define CAN_F8R1_FB29_Pos (29U)
3423#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3424#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3425#define CAN_F8R1_FB30_Pos (30U)
3426#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3427#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3428#define CAN_F8R1_FB31_Pos (31U)
3429#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3430#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3431
3432/******************* Bit definition for CAN_F9R1 register *******************/
3433#define CAN_F9R1_FB0_Pos (0U)
3434#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3435#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3436#define CAN_F9R1_FB1_Pos (1U)
3437#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3438#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3439#define CAN_F9R1_FB2_Pos (2U)
3440#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3441#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3442#define CAN_F9R1_FB3_Pos (3U)
3443#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3444#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3445#define CAN_F9R1_FB4_Pos (4U)
3446#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3447#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3448#define CAN_F9R1_FB5_Pos (5U)
3449#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3450#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3451#define CAN_F9R1_FB6_Pos (6U)
3452#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3453#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3454#define CAN_F9R1_FB7_Pos (7U)
3455#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3456#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3457#define CAN_F9R1_FB8_Pos (8U)
3458#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3459#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3460#define CAN_F9R1_FB9_Pos (9U)
3461#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3462#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3463#define CAN_F9R1_FB10_Pos (10U)
3464#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3465#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3466#define CAN_F9R1_FB11_Pos (11U)
3467#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3468#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3469#define CAN_F9R1_FB12_Pos (12U)
3470#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3471#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3472#define CAN_F9R1_FB13_Pos (13U)
3473#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3474#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3475#define CAN_F9R1_FB14_Pos (14U)
3476#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3477#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3478#define CAN_F9R1_FB15_Pos (15U)
3479#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3480#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3481#define CAN_F9R1_FB16_Pos (16U)
3482#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3483#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3484#define CAN_F9R1_FB17_Pos (17U)
3485#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3486#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3487#define CAN_F9R1_FB18_Pos (18U)
3488#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3489#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3490#define CAN_F9R1_FB19_Pos (19U)
3491#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3492#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3493#define CAN_F9R1_FB20_Pos (20U)
3494#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3495#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3496#define CAN_F9R1_FB21_Pos (21U)
3497#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3498#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3499#define CAN_F9R1_FB22_Pos (22U)
3500#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3501#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3502#define CAN_F9R1_FB23_Pos (23U)
3503#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3504#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3505#define CAN_F9R1_FB24_Pos (24U)
3506#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3507#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3508#define CAN_F9R1_FB25_Pos (25U)
3509#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3510#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3511#define CAN_F9R1_FB26_Pos (26U)
3512#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3513#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3514#define CAN_F9R1_FB27_Pos (27U)
3515#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3516#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3517#define CAN_F9R1_FB28_Pos (28U)
3518#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3519#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3520#define CAN_F9R1_FB29_Pos (29U)
3521#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3522#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3523#define CAN_F9R1_FB30_Pos (30U)
3524#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3525#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3526#define CAN_F9R1_FB31_Pos (31U)
3527#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3528#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3529
3530/******************* Bit definition for CAN_F10R1 register ******************/
3531#define CAN_F10R1_FB0_Pos (0U)
3532#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3533#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3534#define CAN_F10R1_FB1_Pos (1U)
3535#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3536#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3537#define CAN_F10R1_FB2_Pos (2U)
3538#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3539#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3540#define CAN_F10R1_FB3_Pos (3U)
3541#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3542#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3543#define CAN_F10R1_FB4_Pos (4U)
3544#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3545#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3546#define CAN_F10R1_FB5_Pos (5U)
3547#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3548#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3549#define CAN_F10R1_FB6_Pos (6U)
3550#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3551#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3552#define CAN_F10R1_FB7_Pos (7U)
3553#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3554#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3555#define CAN_F10R1_FB8_Pos (8U)
3556#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3557#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3558#define CAN_F10R1_FB9_Pos (9U)
3559#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3560#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3561#define CAN_F10R1_FB10_Pos (10U)
3562#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3563#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3564#define CAN_F10R1_FB11_Pos (11U)
3565#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3566#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3567#define CAN_F10R1_FB12_Pos (12U)
3568#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3569#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3570#define CAN_F10R1_FB13_Pos (13U)
3571#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3572#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3573#define CAN_F10R1_FB14_Pos (14U)
3574#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3575#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3576#define CAN_F10R1_FB15_Pos (15U)
3577#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3578#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3579#define CAN_F10R1_FB16_Pos (16U)
3580#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3581#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3582#define CAN_F10R1_FB17_Pos (17U)
3583#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3584#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3585#define CAN_F10R1_FB18_Pos (18U)
3586#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3587#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3588#define CAN_F10R1_FB19_Pos (19U)
3589#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3590#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3591#define CAN_F10R1_FB20_Pos (20U)
3592#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3593#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3594#define CAN_F10R1_FB21_Pos (21U)
3595#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3596#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3597#define CAN_F10R1_FB22_Pos (22U)
3598#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3599#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3600#define CAN_F10R1_FB23_Pos (23U)
3601#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3602#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3603#define CAN_F10R1_FB24_Pos (24U)
3604#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3605#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3606#define CAN_F10R1_FB25_Pos (25U)
3607#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3608#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3609#define CAN_F10R1_FB26_Pos (26U)
3610#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3611#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3612#define CAN_F10R1_FB27_Pos (27U)
3613#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3614#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3615#define CAN_F10R1_FB28_Pos (28U)
3616#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3617#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3618#define CAN_F10R1_FB29_Pos (29U)
3619#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3620#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3621#define CAN_F10R1_FB30_Pos (30U)
3622#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3623#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3624#define CAN_F10R1_FB31_Pos (31U)
3625#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3626#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3627
3628/******************* Bit definition for CAN_F11R1 register ******************/
3629#define CAN_F11R1_FB0_Pos (0U)
3630#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3631#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3632#define CAN_F11R1_FB1_Pos (1U)
3633#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3634#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3635#define CAN_F11R1_FB2_Pos (2U)
3636#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3637#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3638#define CAN_F11R1_FB3_Pos (3U)
3639#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3640#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3641#define CAN_F11R1_FB4_Pos (4U)
3642#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3643#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3644#define CAN_F11R1_FB5_Pos (5U)
3645#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3646#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3647#define CAN_F11R1_FB6_Pos (6U)
3648#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3649#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3650#define CAN_F11R1_FB7_Pos (7U)
3651#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3652#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3653#define CAN_F11R1_FB8_Pos (8U)
3654#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3655#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3656#define CAN_F11R1_FB9_Pos (9U)
3657#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3658#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3659#define CAN_F11R1_FB10_Pos (10U)
3660#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3661#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3662#define CAN_F11R1_FB11_Pos (11U)
3663#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3664#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3665#define CAN_F11R1_FB12_Pos (12U)
3666#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3667#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3668#define CAN_F11R1_FB13_Pos (13U)
3669#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3670#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3671#define CAN_F11R1_FB14_Pos (14U)
3672#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3673#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3674#define CAN_F11R1_FB15_Pos (15U)
3675#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3676#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3677#define CAN_F11R1_FB16_Pos (16U)
3678#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3679#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3680#define CAN_F11R1_FB17_Pos (17U)
3681#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3682#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3683#define CAN_F11R1_FB18_Pos (18U)
3684#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3685#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3686#define CAN_F11R1_FB19_Pos (19U)
3687#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3688#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3689#define CAN_F11R1_FB20_Pos (20U)
3690#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3691#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3692#define CAN_F11R1_FB21_Pos (21U)
3693#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3694#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3695#define CAN_F11R1_FB22_Pos (22U)
3696#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3697#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3698#define CAN_F11R1_FB23_Pos (23U)
3699#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3700#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3701#define CAN_F11R1_FB24_Pos (24U)
3702#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3703#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3704#define CAN_F11R1_FB25_Pos (25U)
3705#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3706#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3707#define CAN_F11R1_FB26_Pos (26U)
3708#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3709#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3710#define CAN_F11R1_FB27_Pos (27U)
3711#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3712#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3713#define CAN_F11R1_FB28_Pos (28U)
3714#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3715#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3716#define CAN_F11R1_FB29_Pos (29U)
3717#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3718#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3719#define CAN_F11R1_FB30_Pos (30U)
3720#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3721#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3722#define CAN_F11R1_FB31_Pos (31U)
3723#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3724#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3725
3726/******************* Bit definition for CAN_F12R1 register ******************/
3727#define CAN_F12R1_FB0_Pos (0U)
3728#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3729#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3730#define CAN_F12R1_FB1_Pos (1U)
3731#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3732#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3733#define CAN_F12R1_FB2_Pos (2U)
3734#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3735#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3736#define CAN_F12R1_FB3_Pos (3U)
3737#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3738#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3739#define CAN_F12R1_FB4_Pos (4U)
3740#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3741#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3742#define CAN_F12R1_FB5_Pos (5U)
3743#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3744#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3745#define CAN_F12R1_FB6_Pos (6U)
3746#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3747#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3748#define CAN_F12R1_FB7_Pos (7U)
3749#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3750#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3751#define CAN_F12R1_FB8_Pos (8U)
3752#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3753#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3754#define CAN_F12R1_FB9_Pos (9U)
3755#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3756#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3757#define CAN_F12R1_FB10_Pos (10U)
3758#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3759#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3760#define CAN_F12R1_FB11_Pos (11U)
3761#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3762#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3763#define CAN_F12R1_FB12_Pos (12U)
3764#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3765#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3766#define CAN_F12R1_FB13_Pos (13U)
3767#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3768#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3769#define CAN_F12R1_FB14_Pos (14U)
3770#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3771#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3772#define CAN_F12R1_FB15_Pos (15U)
3773#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3774#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3775#define CAN_F12R1_FB16_Pos (16U)
3776#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3777#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3778#define CAN_F12R1_FB17_Pos (17U)
3779#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3780#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3781#define CAN_F12R1_FB18_Pos (18U)
3782#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3783#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3784#define CAN_F12R1_FB19_Pos (19U)
3785#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3786#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3787#define CAN_F12R1_FB20_Pos (20U)
3788#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3789#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3790#define CAN_F12R1_FB21_Pos (21U)
3791#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3792#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3793#define CAN_F12R1_FB22_Pos (22U)
3794#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3795#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3796#define CAN_F12R1_FB23_Pos (23U)
3797#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3798#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3799#define CAN_F12R1_FB24_Pos (24U)
3800#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3801#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3802#define CAN_F12R1_FB25_Pos (25U)
3803#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3804#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3805#define CAN_F12R1_FB26_Pos (26U)
3806#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3807#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3808#define CAN_F12R1_FB27_Pos (27U)
3809#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3810#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3811#define CAN_F12R1_FB28_Pos (28U)
3812#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3813#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3814#define CAN_F12R1_FB29_Pos (29U)
3815#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3816#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3817#define CAN_F12R1_FB30_Pos (30U)
3818#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3819#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3820#define CAN_F12R1_FB31_Pos (31U)
3821#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3822#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3823
3824/******************* Bit definition for CAN_F13R1 register ******************/
3825#define CAN_F13R1_FB0_Pos (0U)
3826#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3827#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3828#define CAN_F13R1_FB1_Pos (1U)
3829#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3830#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3831#define CAN_F13R1_FB2_Pos (2U)
3832#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3833#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3834#define CAN_F13R1_FB3_Pos (3U)
3835#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3836#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3837#define CAN_F13R1_FB4_Pos (4U)
3838#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3839#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3840#define CAN_F13R1_FB5_Pos (5U)
3841#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3842#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3843#define CAN_F13R1_FB6_Pos (6U)
3844#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3845#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3846#define CAN_F13R1_FB7_Pos (7U)
3847#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3848#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3849#define CAN_F13R1_FB8_Pos (8U)
3850#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3851#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3852#define CAN_F13R1_FB9_Pos (9U)
3853#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3854#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3855#define CAN_F13R1_FB10_Pos (10U)
3856#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3857#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3858#define CAN_F13R1_FB11_Pos (11U)
3859#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3860#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3861#define CAN_F13R1_FB12_Pos (12U)
3862#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3863#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3864#define CAN_F13R1_FB13_Pos (13U)
3865#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3866#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
3867#define CAN_F13R1_FB14_Pos (14U)
3868#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
3869#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
3870#define CAN_F13R1_FB15_Pos (15U)
3871#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
3872#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
3873#define CAN_F13R1_FB16_Pos (16U)
3874#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
3875#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
3876#define CAN_F13R1_FB17_Pos (17U)
3877#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
3878#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
3879#define CAN_F13R1_FB18_Pos (18U)
3880#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
3881#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
3882#define CAN_F13R1_FB19_Pos (19U)
3883#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
3884#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
3885#define CAN_F13R1_FB20_Pos (20U)
3886#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
3887#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
3888#define CAN_F13R1_FB21_Pos (21U)
3889#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
3890#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
3891#define CAN_F13R1_FB22_Pos (22U)
3892#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
3893#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
3894#define CAN_F13R1_FB23_Pos (23U)
3895#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
3896#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
3897#define CAN_F13R1_FB24_Pos (24U)
3898#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
3899#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
3900#define CAN_F13R1_FB25_Pos (25U)
3901#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
3902#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
3903#define CAN_F13R1_FB26_Pos (26U)
3904#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
3905#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
3906#define CAN_F13R1_FB27_Pos (27U)
3907#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
3908#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
3909#define CAN_F13R1_FB28_Pos (28U)
3910#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
3911#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
3912#define CAN_F13R1_FB29_Pos (29U)
3913#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
3914#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
3915#define CAN_F13R1_FB30_Pos (30U)
3916#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
3917#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
3918#define CAN_F13R1_FB31_Pos (31U)
3919#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
3920#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
3921
3922/******************* Bit definition for CAN_F0R2 register *******************/
3923#define CAN_F0R2_FB0_Pos (0U)
3924#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
3925#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
3926#define CAN_F0R2_FB1_Pos (1U)
3927#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
3928#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
3929#define CAN_F0R2_FB2_Pos (2U)
3930#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
3931#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
3932#define CAN_F0R2_FB3_Pos (3U)
3933#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
3934#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
3935#define CAN_F0R2_FB4_Pos (4U)
3936#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
3937#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
3938#define CAN_F0R2_FB5_Pos (5U)
3939#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
3940#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
3941#define CAN_F0R2_FB6_Pos (6U)
3942#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
3943#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
3944#define CAN_F0R2_FB7_Pos (7U)
3945#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
3946#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
3947#define CAN_F0R2_FB8_Pos (8U)
3948#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
3949#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
3950#define CAN_F0R2_FB9_Pos (9U)
3951#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
3952#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
3953#define CAN_F0R2_FB10_Pos (10U)
3954#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
3955#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
3956#define CAN_F0R2_FB11_Pos (11U)
3957#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
3958#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
3959#define CAN_F0R2_FB12_Pos (12U)
3960#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
3961#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
3962#define CAN_F0R2_FB13_Pos (13U)
3963#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
3964#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
3965#define CAN_F0R2_FB14_Pos (14U)
3966#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
3967#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
3968#define CAN_F0R2_FB15_Pos (15U)
3969#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
3970#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
3971#define CAN_F0R2_FB16_Pos (16U)
3972#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
3973#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
3974#define CAN_F0R2_FB17_Pos (17U)
3975#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
3976#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
3977#define CAN_F0R2_FB18_Pos (18U)
3978#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
3979#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
3980#define CAN_F0R2_FB19_Pos (19U)
3981#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
3982#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
3983#define CAN_F0R2_FB20_Pos (20U)
3984#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
3985#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
3986#define CAN_F0R2_FB21_Pos (21U)
3987#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
3988#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
3989#define CAN_F0R2_FB22_Pos (22U)
3990#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
3991#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
3992#define CAN_F0R2_FB23_Pos (23U)
3993#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
3994#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
3995#define CAN_F0R2_FB24_Pos (24U)
3996#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
3997#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
3998#define CAN_F0R2_FB25_Pos (25U)
3999#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4000#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4001#define CAN_F0R2_FB26_Pos (26U)
4002#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4003#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4004#define CAN_F0R2_FB27_Pos (27U)
4005#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4006#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4007#define CAN_F0R2_FB28_Pos (28U)
4008#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4009#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4010#define CAN_F0R2_FB29_Pos (29U)
4011#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4012#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4013#define CAN_F0R2_FB30_Pos (30U)
4014#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4015#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4016#define CAN_F0R2_FB31_Pos (31U)
4017#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4018#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4019
4020/******************* Bit definition for CAN_F1R2 register *******************/
4021#define CAN_F1R2_FB0_Pos (0U)
4022#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4023#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4024#define CAN_F1R2_FB1_Pos (1U)
4025#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4026#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4027#define CAN_F1R2_FB2_Pos (2U)
4028#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4029#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4030#define CAN_F1R2_FB3_Pos (3U)
4031#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4032#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4033#define CAN_F1R2_FB4_Pos (4U)
4034#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4035#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4036#define CAN_F1R2_FB5_Pos (5U)
4037#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4038#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4039#define CAN_F1R2_FB6_Pos (6U)
4040#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4041#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4042#define CAN_F1R2_FB7_Pos (7U)
4043#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4044#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4045#define CAN_F1R2_FB8_Pos (8U)
4046#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4047#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4048#define CAN_F1R2_FB9_Pos (9U)
4049#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4050#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4051#define CAN_F1R2_FB10_Pos (10U)
4052#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4053#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4054#define CAN_F1R2_FB11_Pos (11U)
4055#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4056#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4057#define CAN_F1R2_FB12_Pos (12U)
4058#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4059#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4060#define CAN_F1R2_FB13_Pos (13U)
4061#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4062#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4063#define CAN_F1R2_FB14_Pos (14U)
4064#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4065#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4066#define CAN_F1R2_FB15_Pos (15U)
4067#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4068#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4069#define CAN_F1R2_FB16_Pos (16U)
4070#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4071#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4072#define CAN_F1R2_FB17_Pos (17U)
4073#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4074#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4075#define CAN_F1R2_FB18_Pos (18U)
4076#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4077#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4078#define CAN_F1R2_FB19_Pos (19U)
4079#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4080#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4081#define CAN_F1R2_FB20_Pos (20U)
4082#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4083#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4084#define CAN_F1R2_FB21_Pos (21U)
4085#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4086#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4087#define CAN_F1R2_FB22_Pos (22U)
4088#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4089#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4090#define CAN_F1R2_FB23_Pos (23U)
4091#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4092#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4093#define CAN_F1R2_FB24_Pos (24U)
4094#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4095#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4096#define CAN_F1R2_FB25_Pos (25U)
4097#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4098#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4099#define CAN_F1R2_FB26_Pos (26U)
4100#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4101#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4102#define CAN_F1R2_FB27_Pos (27U)
4103#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4104#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4105#define CAN_F1R2_FB28_Pos (28U)
4106#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4107#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4108#define CAN_F1R2_FB29_Pos (29U)
4109#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4110#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4111#define CAN_F1R2_FB30_Pos (30U)
4112#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4113#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4114#define CAN_F1R2_FB31_Pos (31U)
4115#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4116#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4117
4118/******************* Bit definition for CAN_F2R2 register *******************/
4119#define CAN_F2R2_FB0_Pos (0U)
4120#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4121#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4122#define CAN_F2R2_FB1_Pos (1U)
4123#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4124#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4125#define CAN_F2R2_FB2_Pos (2U)
4126#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4127#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4128#define CAN_F2R2_FB3_Pos (3U)
4129#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4130#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4131#define CAN_F2R2_FB4_Pos (4U)
4132#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4133#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4134#define CAN_F2R2_FB5_Pos (5U)
4135#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4136#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4137#define CAN_F2R2_FB6_Pos (6U)
4138#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4139#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4140#define CAN_F2R2_FB7_Pos (7U)
4141#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4142#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4143#define CAN_F2R2_FB8_Pos (8U)
4144#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4145#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4146#define CAN_F2R2_FB9_Pos (9U)
4147#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4148#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4149#define CAN_F2R2_FB10_Pos (10U)
4150#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4151#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4152#define CAN_F2R2_FB11_Pos (11U)
4153#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4154#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4155#define CAN_F2R2_FB12_Pos (12U)
4156#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4157#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4158#define CAN_F2R2_FB13_Pos (13U)
4159#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4160#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4161#define CAN_F2R2_FB14_Pos (14U)
4162#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4163#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4164#define CAN_F2R2_FB15_Pos (15U)
4165#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4166#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4167#define CAN_F2R2_FB16_Pos (16U)
4168#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4169#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4170#define CAN_F2R2_FB17_Pos (17U)
4171#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4172#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4173#define CAN_F2R2_FB18_Pos (18U)
4174#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4175#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4176#define CAN_F2R2_FB19_Pos (19U)
4177#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4178#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4179#define CAN_F2R2_FB20_Pos (20U)
4180#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4181#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4182#define CAN_F2R2_FB21_Pos (21U)
4183#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4184#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4185#define CAN_F2R2_FB22_Pos (22U)
4186#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4187#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4188#define CAN_F2R2_FB23_Pos (23U)
4189#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4190#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4191#define CAN_F2R2_FB24_Pos (24U)
4192#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4193#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4194#define CAN_F2R2_FB25_Pos (25U)
4195#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4196#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4197#define CAN_F2R2_FB26_Pos (26U)
4198#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4199#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4200#define CAN_F2R2_FB27_Pos (27U)
4201#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4202#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4203#define CAN_F2R2_FB28_Pos (28U)
4204#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4205#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4206#define CAN_F2R2_FB29_Pos (29U)
4207#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4208#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4209#define CAN_F2R2_FB30_Pos (30U)
4210#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4211#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4212#define CAN_F2R2_FB31_Pos (31U)
4213#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4214#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4215
4216/******************* Bit definition for CAN_F3R2 register *******************/
4217#define CAN_F3R2_FB0_Pos (0U)
4218#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4219#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4220#define CAN_F3R2_FB1_Pos (1U)
4221#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4222#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4223#define CAN_F3R2_FB2_Pos (2U)
4224#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4225#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4226#define CAN_F3R2_FB3_Pos (3U)
4227#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4228#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4229#define CAN_F3R2_FB4_Pos (4U)
4230#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4231#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4232#define CAN_F3R2_FB5_Pos (5U)
4233#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4234#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4235#define CAN_F3R2_FB6_Pos (6U)
4236#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4237#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4238#define CAN_F3R2_FB7_Pos (7U)
4239#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4240#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4241#define CAN_F3R2_FB8_Pos (8U)
4242#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4243#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4244#define CAN_F3R2_FB9_Pos (9U)
4245#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4246#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4247#define CAN_F3R2_FB10_Pos (10U)
4248#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4249#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4250#define CAN_F3R2_FB11_Pos (11U)
4251#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4252#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4253#define CAN_F3R2_FB12_Pos (12U)
4254#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4255#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4256#define CAN_F3R2_FB13_Pos (13U)
4257#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4258#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4259#define CAN_F3R2_FB14_Pos (14U)
4260#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4261#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4262#define CAN_F3R2_FB15_Pos (15U)
4263#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4264#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4265#define CAN_F3R2_FB16_Pos (16U)
4266#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4267#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4268#define CAN_F3R2_FB17_Pos (17U)
4269#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4270#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4271#define CAN_F3R2_FB18_Pos (18U)
4272#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4273#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4274#define CAN_F3R2_FB19_Pos (19U)
4275#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4276#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4277#define CAN_F3R2_FB20_Pos (20U)
4278#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4279#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4280#define CAN_F3R2_FB21_Pos (21U)
4281#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4282#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4283#define CAN_F3R2_FB22_Pos (22U)
4284#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4285#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4286#define CAN_F3R2_FB23_Pos (23U)
4287#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4288#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4289#define CAN_F3R2_FB24_Pos (24U)
4290#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4291#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4292#define CAN_F3R2_FB25_Pos (25U)
4293#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4294#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4295#define CAN_F3R2_FB26_Pos (26U)
4296#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4297#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4298#define CAN_F3R2_FB27_Pos (27U)
4299#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4300#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4301#define CAN_F3R2_FB28_Pos (28U)
4302#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4303#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4304#define CAN_F3R2_FB29_Pos (29U)
4305#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4306#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4307#define CAN_F3R2_FB30_Pos (30U)
4308#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4309#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4310#define CAN_F3R2_FB31_Pos (31U)
4311#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4312#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4313
4314/******************* Bit definition for CAN_F4R2 register *******************/
4315#define CAN_F4R2_FB0_Pos (0U)
4316#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4317#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4318#define CAN_F4R2_FB1_Pos (1U)
4319#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4320#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4321#define CAN_F4R2_FB2_Pos (2U)
4322#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4323#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4324#define CAN_F4R2_FB3_Pos (3U)
4325#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4326#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4327#define CAN_F4R2_FB4_Pos (4U)
4328#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4329#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4330#define CAN_F4R2_FB5_Pos (5U)
4331#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4332#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4333#define CAN_F4R2_FB6_Pos (6U)
4334#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4335#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4336#define CAN_F4R2_FB7_Pos (7U)
4337#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4338#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4339#define CAN_F4R2_FB8_Pos (8U)
4340#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4341#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4342#define CAN_F4R2_FB9_Pos (9U)
4343#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4344#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4345#define CAN_F4R2_FB10_Pos (10U)
4346#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4347#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4348#define CAN_F4R2_FB11_Pos (11U)
4349#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4350#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4351#define CAN_F4R2_FB12_Pos (12U)
4352#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4353#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4354#define CAN_F4R2_FB13_Pos (13U)
4355#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4356#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4357#define CAN_F4R2_FB14_Pos (14U)
4358#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4359#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4360#define CAN_F4R2_FB15_Pos (15U)
4361#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4362#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4363#define CAN_F4R2_FB16_Pos (16U)
4364#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4365#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4366#define CAN_F4R2_FB17_Pos (17U)
4367#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4368#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4369#define CAN_F4R2_FB18_Pos (18U)
4370#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4371#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4372#define CAN_F4R2_FB19_Pos (19U)
4373#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4374#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4375#define CAN_F4R2_FB20_Pos (20U)
4376#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4377#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4378#define CAN_F4R2_FB21_Pos (21U)
4379#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4380#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4381#define CAN_F4R2_FB22_Pos (22U)
4382#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4383#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4384#define CAN_F4R2_FB23_Pos (23U)
4385#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4386#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4387#define CAN_F4R2_FB24_Pos (24U)
4388#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4389#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4390#define CAN_F4R2_FB25_Pos (25U)
4391#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4392#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4393#define CAN_F4R2_FB26_Pos (26U)
4394#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4395#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4396#define CAN_F4R2_FB27_Pos (27U)
4397#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4398#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4399#define CAN_F4R2_FB28_Pos (28U)
4400#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4401#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4402#define CAN_F4R2_FB29_Pos (29U)
4403#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4404#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4405#define CAN_F4R2_FB30_Pos (30U)
4406#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4407#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4408#define CAN_F4R2_FB31_Pos (31U)
4409#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4410#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4411
4412/******************* Bit definition for CAN_F5R2 register *******************/
4413#define CAN_F5R2_FB0_Pos (0U)
4414#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4415#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4416#define CAN_F5R2_FB1_Pos (1U)
4417#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4418#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4419#define CAN_F5R2_FB2_Pos (2U)
4420#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4421#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4422#define CAN_F5R2_FB3_Pos (3U)
4423#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4424#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4425#define CAN_F5R2_FB4_Pos (4U)
4426#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4427#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4428#define CAN_F5R2_FB5_Pos (5U)
4429#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4430#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4431#define CAN_F5R2_FB6_Pos (6U)
4432#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4433#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4434#define CAN_F5R2_FB7_Pos (7U)
4435#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4436#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4437#define CAN_F5R2_FB8_Pos (8U)
4438#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4439#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4440#define CAN_F5R2_FB9_Pos (9U)
4441#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4442#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4443#define CAN_F5R2_FB10_Pos (10U)
4444#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4445#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4446#define CAN_F5R2_FB11_Pos (11U)
4447#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4448#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4449#define CAN_F5R2_FB12_Pos (12U)
4450#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4451#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4452#define CAN_F5R2_FB13_Pos (13U)
4453#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4454#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4455#define CAN_F5R2_FB14_Pos (14U)
4456#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4457#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4458#define CAN_F5R2_FB15_Pos (15U)
4459#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4460#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4461#define CAN_F5R2_FB16_Pos (16U)
4462#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4463#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4464#define CAN_F5R2_FB17_Pos (17U)
4465#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4466#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4467#define CAN_F5R2_FB18_Pos (18U)
4468#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4469#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4470#define CAN_F5R2_FB19_Pos (19U)
4471#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4472#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4473#define CAN_F5R2_FB20_Pos (20U)
4474#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4475#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4476#define CAN_F5R2_FB21_Pos (21U)
4477#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4478#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4479#define CAN_F5R2_FB22_Pos (22U)
4480#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4481#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4482#define CAN_F5R2_FB23_Pos (23U)
4483#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4484#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4485#define CAN_F5R2_FB24_Pos (24U)
4486#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4487#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4488#define CAN_F5R2_FB25_Pos (25U)
4489#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4490#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4491#define CAN_F5R2_FB26_Pos (26U)
4492#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4493#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4494#define CAN_F5R2_FB27_Pos (27U)
4495#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4496#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4497#define CAN_F5R2_FB28_Pos (28U)
4498#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4499#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4500#define CAN_F5R2_FB29_Pos (29U)
4501#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4502#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4503#define CAN_F5R2_FB30_Pos (30U)
4504#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4505#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4506#define CAN_F5R2_FB31_Pos (31U)
4507#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4508#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4509
4510/******************* Bit definition for CAN_F6R2 register *******************/
4511#define CAN_F6R2_FB0_Pos (0U)
4512#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4513#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4514#define CAN_F6R2_FB1_Pos (1U)
4515#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4516#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4517#define CAN_F6R2_FB2_Pos (2U)
4518#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4519#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4520#define CAN_F6R2_FB3_Pos (3U)
4521#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4522#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4523#define CAN_F6R2_FB4_Pos (4U)
4524#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4525#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4526#define CAN_F6R2_FB5_Pos (5U)
4527#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4528#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4529#define CAN_F6R2_FB6_Pos (6U)
4530#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4531#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4532#define CAN_F6R2_FB7_Pos (7U)
4533#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4534#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4535#define CAN_F6R2_FB8_Pos (8U)
4536#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4537#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4538#define CAN_F6R2_FB9_Pos (9U)
4539#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4540#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4541#define CAN_F6R2_FB10_Pos (10U)
4542#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4543#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4544#define CAN_F6R2_FB11_Pos (11U)
4545#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4546#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4547#define CAN_F6R2_FB12_Pos (12U)
4548#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4549#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4550#define CAN_F6R2_FB13_Pos (13U)
4551#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4552#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4553#define CAN_F6R2_FB14_Pos (14U)
4554#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4555#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4556#define CAN_F6R2_FB15_Pos (15U)
4557#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4558#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4559#define CAN_F6R2_FB16_Pos (16U)
4560#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4561#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4562#define CAN_F6R2_FB17_Pos (17U)
4563#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4564#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4565#define CAN_F6R2_FB18_Pos (18U)
4566#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4567#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4568#define CAN_F6R2_FB19_Pos (19U)
4569#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4570#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4571#define CAN_F6R2_FB20_Pos (20U)
4572#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4573#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4574#define CAN_F6R2_FB21_Pos (21U)
4575#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4576#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4577#define CAN_F6R2_FB22_Pos (22U)
4578#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4579#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4580#define CAN_F6R2_FB23_Pos (23U)
4581#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4582#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4583#define CAN_F6R2_FB24_Pos (24U)
4584#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4585#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4586#define CAN_F6R2_FB25_Pos (25U)
4587#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4588#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4589#define CAN_F6R2_FB26_Pos (26U)
4590#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4591#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4592#define CAN_F6R2_FB27_Pos (27U)
4593#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4594#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4595#define CAN_F6R2_FB28_Pos (28U)
4596#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4597#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4598#define CAN_F6R2_FB29_Pos (29U)
4599#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4600#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4601#define CAN_F6R2_FB30_Pos (30U)
4602#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4603#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4604#define CAN_F6R2_FB31_Pos (31U)
4605#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4606#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4607
4608/******************* Bit definition for CAN_F7R2 register *******************/
4609#define CAN_F7R2_FB0_Pos (0U)
4610#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4611#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4612#define CAN_F7R2_FB1_Pos (1U)
4613#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4614#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4615#define CAN_F7R2_FB2_Pos (2U)
4616#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4617#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4618#define CAN_F7R2_FB3_Pos (3U)
4619#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4620#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4621#define CAN_F7R2_FB4_Pos (4U)
4622#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4623#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4624#define CAN_F7R2_FB5_Pos (5U)
4625#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4626#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4627#define CAN_F7R2_FB6_Pos (6U)
4628#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4629#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4630#define CAN_F7R2_FB7_Pos (7U)
4631#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4632#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4633#define CAN_F7R2_FB8_Pos (8U)
4634#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4635#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4636#define CAN_F7R2_FB9_Pos (9U)
4637#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4638#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4639#define CAN_F7R2_FB10_Pos (10U)
4640#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4641#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4642#define CAN_F7R2_FB11_Pos (11U)
4643#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4644#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4645#define CAN_F7R2_FB12_Pos (12U)
4646#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4647#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4648#define CAN_F7R2_FB13_Pos (13U)
4649#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4650#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4651#define CAN_F7R2_FB14_Pos (14U)
4652#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4653#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4654#define CAN_F7R2_FB15_Pos (15U)
4655#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4656#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4657#define CAN_F7R2_FB16_Pos (16U)
4658#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4659#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4660#define CAN_F7R2_FB17_Pos (17U)
4661#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4662#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4663#define CAN_F7R2_FB18_Pos (18U)
4664#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4665#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4666#define CAN_F7R2_FB19_Pos (19U)
4667#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4668#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4669#define CAN_F7R2_FB20_Pos (20U)
4670#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4671#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4672#define CAN_F7R2_FB21_Pos (21U)
4673#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4674#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4675#define CAN_F7R2_FB22_Pos (22U)
4676#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4677#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4678#define CAN_F7R2_FB23_Pos (23U)
4679#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4680#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4681#define CAN_F7R2_FB24_Pos (24U)
4682#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4683#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4684#define CAN_F7R2_FB25_Pos (25U)
4685#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4686#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4687#define CAN_F7R2_FB26_Pos (26U)
4688#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4689#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4690#define CAN_F7R2_FB27_Pos (27U)
4691#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4692#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4693#define CAN_F7R2_FB28_Pos (28U)
4694#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4695#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4696#define CAN_F7R2_FB29_Pos (29U)
4697#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4698#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4699#define CAN_F7R2_FB30_Pos (30U)
4700#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4701#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4702#define CAN_F7R2_FB31_Pos (31U)
4703#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4704#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4705
4706/******************* Bit definition for CAN_F8R2 register *******************/
4707#define CAN_F8R2_FB0_Pos (0U)
4708#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4709#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4710#define CAN_F8R2_FB1_Pos (1U)
4711#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4712#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4713#define CAN_F8R2_FB2_Pos (2U)
4714#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4715#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4716#define CAN_F8R2_FB3_Pos (3U)
4717#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4718#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4719#define CAN_F8R2_FB4_Pos (4U)
4720#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4721#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4722#define CAN_F8R2_FB5_Pos (5U)
4723#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4724#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4725#define CAN_F8R2_FB6_Pos (6U)
4726#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4727#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4728#define CAN_F8R2_FB7_Pos (7U)
4729#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4730#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4731#define CAN_F8R2_FB8_Pos (8U)
4732#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4733#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4734#define CAN_F8R2_FB9_Pos (9U)
4735#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4736#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4737#define CAN_F8R2_FB10_Pos (10U)
4738#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4739#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4740#define CAN_F8R2_FB11_Pos (11U)
4741#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4742#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4743#define CAN_F8R2_FB12_Pos (12U)
4744#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4745#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4746#define CAN_F8R2_FB13_Pos (13U)
4747#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4748#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4749#define CAN_F8R2_FB14_Pos (14U)
4750#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4751#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4752#define CAN_F8R2_FB15_Pos (15U)
4753#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4754#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4755#define CAN_F8R2_FB16_Pos (16U)
4756#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4757#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4758#define CAN_F8R2_FB17_Pos (17U)
4759#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4760#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4761#define CAN_F8R2_FB18_Pos (18U)
4762#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4763#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4764#define CAN_F8R2_FB19_Pos (19U)
4765#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4766#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4767#define CAN_F8R2_FB20_Pos (20U)
4768#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4769#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4770#define CAN_F8R2_FB21_Pos (21U)
4771#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4772#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4773#define CAN_F8R2_FB22_Pos (22U)
4774#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4775#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4776#define CAN_F8R2_FB23_Pos (23U)
4777#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4778#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4779#define CAN_F8R2_FB24_Pos (24U)
4780#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4781#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4782#define CAN_F8R2_FB25_Pos (25U)
4783#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4784#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4785#define CAN_F8R2_FB26_Pos (26U)
4786#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4787#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4788#define CAN_F8R2_FB27_Pos (27U)
4789#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4790#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4791#define CAN_F8R2_FB28_Pos (28U)
4792#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4793#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4794#define CAN_F8R2_FB29_Pos (29U)
4795#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4796#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4797#define CAN_F8R2_FB30_Pos (30U)
4798#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4799#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4800#define CAN_F8R2_FB31_Pos (31U)
4801#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4802#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4803
4804/******************* Bit definition for CAN_F9R2 register *******************/
4805#define CAN_F9R2_FB0_Pos (0U)
4806#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4807#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4808#define CAN_F9R2_FB1_Pos (1U)
4809#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4810#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4811#define CAN_F9R2_FB2_Pos (2U)
4812#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4813#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4814#define CAN_F9R2_FB3_Pos (3U)
4815#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4816#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4817#define CAN_F9R2_FB4_Pos (4U)
4818#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4819#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4820#define CAN_F9R2_FB5_Pos (5U)
4821#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4822#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4823#define CAN_F9R2_FB6_Pos (6U)
4824#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4825#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4826#define CAN_F9R2_FB7_Pos (7U)
4827#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4828#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4829#define CAN_F9R2_FB8_Pos (8U)
4830#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4831#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4832#define CAN_F9R2_FB9_Pos (9U)
4833#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4834#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4835#define CAN_F9R2_FB10_Pos (10U)
4836#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4837#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4838#define CAN_F9R2_FB11_Pos (11U)
4839#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4840#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4841#define CAN_F9R2_FB12_Pos (12U)
4842#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4843#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4844#define CAN_F9R2_FB13_Pos (13U)
4845#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4846#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4847#define CAN_F9R2_FB14_Pos (14U)
4848#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4849#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4850#define CAN_F9R2_FB15_Pos (15U)
4851#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4852#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4853#define CAN_F9R2_FB16_Pos (16U)
4854#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4855#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4856#define CAN_F9R2_FB17_Pos (17U)
4857#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4858#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4859#define CAN_F9R2_FB18_Pos (18U)
4860#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4861#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4862#define CAN_F9R2_FB19_Pos (19U)
4863#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4864#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4865#define CAN_F9R2_FB20_Pos (20U)
4866#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
4867#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
4868#define CAN_F9R2_FB21_Pos (21U)
4869#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
4870#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
4871#define CAN_F9R2_FB22_Pos (22U)
4872#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
4873#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
4874#define CAN_F9R2_FB23_Pos (23U)
4875#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
4876#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
4877#define CAN_F9R2_FB24_Pos (24U)
4878#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
4879#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
4880#define CAN_F9R2_FB25_Pos (25U)
4881#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
4882#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
4883#define CAN_F9R2_FB26_Pos (26U)
4884#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
4885#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
4886#define CAN_F9R2_FB27_Pos (27U)
4887#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
4888#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
4889#define CAN_F9R2_FB28_Pos (28U)
4890#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
4891#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
4892#define CAN_F9R2_FB29_Pos (29U)
4893#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
4894#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
4895#define CAN_F9R2_FB30_Pos (30U)
4896#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
4897#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
4898#define CAN_F9R2_FB31_Pos (31U)
4899#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
4900#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
4901
4902/******************* Bit definition for CAN_F10R2 register ******************/
4903#define CAN_F10R2_FB0_Pos (0U)
4904#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
4905#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
4906#define CAN_F10R2_FB1_Pos (1U)
4907#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
4908#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
4909#define CAN_F10R2_FB2_Pos (2U)
4910#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
4911#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
4912#define CAN_F10R2_FB3_Pos (3U)
4913#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
4914#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
4915#define CAN_F10R2_FB4_Pos (4U)
4916#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
4917#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
4918#define CAN_F10R2_FB5_Pos (5U)
4919#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
4920#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
4921#define CAN_F10R2_FB6_Pos (6U)
4922#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
4923#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
4924#define CAN_F10R2_FB7_Pos (7U)
4925#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
4926#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
4927#define CAN_F10R2_FB8_Pos (8U)
4928#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
4929#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
4930#define CAN_F10R2_FB9_Pos (9U)
4931#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
4932#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
4933#define CAN_F10R2_FB10_Pos (10U)
4934#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
4935#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
4936#define CAN_F10R2_FB11_Pos (11U)
4937#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
4938#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
4939#define CAN_F10R2_FB12_Pos (12U)
4940#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
4941#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
4942#define CAN_F10R2_FB13_Pos (13U)
4943#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
4944#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
4945#define CAN_F10R2_FB14_Pos (14U)
4946#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
4947#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
4948#define CAN_F10R2_FB15_Pos (15U)
4949#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
4950#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
4951#define CAN_F10R2_FB16_Pos (16U)
4952#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
4953#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
4954#define CAN_F10R2_FB17_Pos (17U)
4955#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
4956#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
4957#define CAN_F10R2_FB18_Pos (18U)
4958#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
4959#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
4960#define CAN_F10R2_FB19_Pos (19U)
4961#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
4962#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
4963#define CAN_F10R2_FB20_Pos (20U)
4964#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
4965#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
4966#define CAN_F10R2_FB21_Pos (21U)
4967#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
4968#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
4969#define CAN_F10R2_FB22_Pos (22U)
4970#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
4971#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
4972#define CAN_F10R2_FB23_Pos (23U)
4973#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
4974#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
4975#define CAN_F10R2_FB24_Pos (24U)
4976#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
4977#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
4978#define CAN_F10R2_FB25_Pos (25U)
4979#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
4980#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
4981#define CAN_F10R2_FB26_Pos (26U)
4982#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
4983#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
4984#define CAN_F10R2_FB27_Pos (27U)
4985#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
4986#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
4987#define CAN_F10R2_FB28_Pos (28U)
4988#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
4989#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
4990#define CAN_F10R2_FB29_Pos (29U)
4991#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
4992#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
4993#define CAN_F10R2_FB30_Pos (30U)
4994#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
4995#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
4996#define CAN_F10R2_FB31_Pos (31U)
4997#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
4998#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
4999
5000/******************* Bit definition for CAN_F11R2 register ******************/
5001#define CAN_F11R2_FB0_Pos (0U)
5002#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5003#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5004#define CAN_F11R2_FB1_Pos (1U)
5005#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5006#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5007#define CAN_F11R2_FB2_Pos (2U)
5008#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5009#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5010#define CAN_F11R2_FB3_Pos (3U)
5011#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5012#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5013#define CAN_F11R2_FB4_Pos (4U)
5014#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5015#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5016#define CAN_F11R2_FB5_Pos (5U)
5017#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5018#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5019#define CAN_F11R2_FB6_Pos (6U)
5020#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5021#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5022#define CAN_F11R2_FB7_Pos (7U)
5023#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5024#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5025#define CAN_F11R2_FB8_Pos (8U)
5026#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5027#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5028#define CAN_F11R2_FB9_Pos (9U)
5029#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5030#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5031#define CAN_F11R2_FB10_Pos (10U)
5032#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5033#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5034#define CAN_F11R2_FB11_Pos (11U)
5035#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5036#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5037#define CAN_F11R2_FB12_Pos (12U)
5038#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5039#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5040#define CAN_F11R2_FB13_Pos (13U)
5041#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5042#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5043#define CAN_F11R2_FB14_Pos (14U)
5044#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5045#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5046#define CAN_F11R2_FB15_Pos (15U)
5047#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5048#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5049#define CAN_F11R2_FB16_Pos (16U)
5050#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5051#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5052#define CAN_F11R2_FB17_Pos (17U)
5053#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5054#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5055#define CAN_F11R2_FB18_Pos (18U)
5056#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5057#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5058#define CAN_F11R2_FB19_Pos (19U)
5059#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5060#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5061#define CAN_F11R2_FB20_Pos (20U)
5062#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5063#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5064#define CAN_F11R2_FB21_Pos (21U)
5065#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5066#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5067#define CAN_F11R2_FB22_Pos (22U)
5068#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5069#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5070#define CAN_F11R2_FB23_Pos (23U)
5071#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5072#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5073#define CAN_F11R2_FB24_Pos (24U)
5074#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5075#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5076#define CAN_F11R2_FB25_Pos (25U)
5077#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5078#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5079#define CAN_F11R2_FB26_Pos (26U)
5080#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5081#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5082#define CAN_F11R2_FB27_Pos (27U)
5083#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5084#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5085#define CAN_F11R2_FB28_Pos (28U)
5086#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5087#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5088#define CAN_F11R2_FB29_Pos (29U)
5089#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5090#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5091#define CAN_F11R2_FB30_Pos (30U)
5092#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5093#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5094#define CAN_F11R2_FB31_Pos (31U)
5095#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5096#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5097
5098/******************* Bit definition for CAN_F12R2 register ******************/
5099#define CAN_F12R2_FB0_Pos (0U)
5100#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5101#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5102#define CAN_F12R2_FB1_Pos (1U)
5103#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5104#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5105#define CAN_F12R2_FB2_Pos (2U)
5106#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5107#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5108#define CAN_F12R2_FB3_Pos (3U)
5109#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5110#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5111#define CAN_F12R2_FB4_Pos (4U)
5112#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5113#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5114#define CAN_F12R2_FB5_Pos (5U)
5115#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5116#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5117#define CAN_F12R2_FB6_Pos (6U)
5118#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5119#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5120#define CAN_F12R2_FB7_Pos (7U)
5121#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5122#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5123#define CAN_F12R2_FB8_Pos (8U)
5124#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5125#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5126#define CAN_F12R2_FB9_Pos (9U)
5127#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5128#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5129#define CAN_F12R2_FB10_Pos (10U)
5130#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5131#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5132#define CAN_F12R2_FB11_Pos (11U)
5133#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5134#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5135#define CAN_F12R2_FB12_Pos (12U)
5136#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5137#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5138#define CAN_F12R2_FB13_Pos (13U)
5139#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5140#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5141#define CAN_F12R2_FB14_Pos (14U)
5142#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5143#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5144#define CAN_F12R2_FB15_Pos (15U)
5145#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5146#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5147#define CAN_F12R2_FB16_Pos (16U)
5148#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5149#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5150#define CAN_F12R2_FB17_Pos (17U)
5151#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5152#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5153#define CAN_F12R2_FB18_Pos (18U)
5154#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5155#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5156#define CAN_F12R2_FB19_Pos (19U)
5157#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5158#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5159#define CAN_F12R2_FB20_Pos (20U)
5160#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5161#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5162#define CAN_F12R2_FB21_Pos (21U)
5163#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5164#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5165#define CAN_F12R2_FB22_Pos (22U)
5166#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5167#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5168#define CAN_F12R2_FB23_Pos (23U)
5169#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5170#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5171#define CAN_F12R2_FB24_Pos (24U)
5172#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5173#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5174#define CAN_F12R2_FB25_Pos (25U)
5175#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5176#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5177#define CAN_F12R2_FB26_Pos (26U)
5178#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5179#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5180#define CAN_F12R2_FB27_Pos (27U)
5181#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5182#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5183#define CAN_F12R2_FB28_Pos (28U)
5184#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5185#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5186#define CAN_F12R2_FB29_Pos (29U)
5187#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5188#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5189#define CAN_F12R2_FB30_Pos (30U)
5190#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5191#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5192#define CAN_F12R2_FB31_Pos (31U)
5193#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5194#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5195
5196/******************* Bit definition for CAN_F13R2 register ******************/
5197#define CAN_F13R2_FB0_Pos (0U)
5198#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5199#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5200#define CAN_F13R2_FB1_Pos (1U)
5201#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5202#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5203#define CAN_F13R2_FB2_Pos (2U)
5204#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5205#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5206#define CAN_F13R2_FB3_Pos (3U)
5207#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5208#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5209#define CAN_F13R2_FB4_Pos (4U)
5210#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5211#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5212#define CAN_F13R2_FB5_Pos (5U)
5213#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5214#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5215#define CAN_F13R2_FB6_Pos (6U)
5216#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5217#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5218#define CAN_F13R2_FB7_Pos (7U)
5219#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5220#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5221#define CAN_F13R2_FB8_Pos (8U)
5222#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5223#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5224#define CAN_F13R2_FB9_Pos (9U)
5225#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5226#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5227#define CAN_F13R2_FB10_Pos (10U)
5228#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5229#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5230#define CAN_F13R2_FB11_Pos (11U)
5231#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5232#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5233#define CAN_F13R2_FB12_Pos (12U)
5234#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5235#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5236#define CAN_F13R2_FB13_Pos (13U)
5237#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5238#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5239#define CAN_F13R2_FB14_Pos (14U)
5240#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5241#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5242#define CAN_F13R2_FB15_Pos (15U)
5243#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5244#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5245#define CAN_F13R2_FB16_Pos (16U)
5246#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5247#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5248#define CAN_F13R2_FB17_Pos (17U)
5249#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5250#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5251#define CAN_F13R2_FB18_Pos (18U)
5252#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5253#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5254#define CAN_F13R2_FB19_Pos (19U)
5255#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5256#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5257#define CAN_F13R2_FB20_Pos (20U)
5258#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5259#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5260#define CAN_F13R2_FB21_Pos (21U)
5261#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5262#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5263#define CAN_F13R2_FB22_Pos (22U)
5264#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5265#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5266#define CAN_F13R2_FB23_Pos (23U)
5267#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5268#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5269#define CAN_F13R2_FB24_Pos (24U)
5270#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5271#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5272#define CAN_F13R2_FB25_Pos (25U)
5273#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5274#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5275#define CAN_F13R2_FB26_Pos (26U)
5276#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5277#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5278#define CAN_F13R2_FB27_Pos (27U)
5279#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5280#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5281#define CAN_F13R2_FB28_Pos (28U)
5282#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5283#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5284#define CAN_F13R2_FB29_Pos (29U)
5285#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5286#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5287#define CAN_F13R2_FB30_Pos (30U)
5288#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5289#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5290#define CAN_F13R2_FB31_Pos (31U)
5291#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5292#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5293
5294/******************************************************************************/
5295/* */
5296/* CRC calculation unit */
5297/* */
5298/******************************************************************************/
5299/******************* Bit definition for CRC_DR register *********************/
5300#define CRC_DR_DR_Pos (0U)
5301#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5302#define CRC_DR_DR CRC_DR_DR_Msk
5303
5304
5305/******************* Bit definition for CRC_IDR register ********************/
5306#define CRC_IDR_IDR_Pos (0U)
5307#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5308#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5309
5310
5311/******************** Bit definition for CRC_CR register ********************/
5312#define CRC_CR_RESET_Pos (0U)
5313#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5314#define CRC_CR_RESET CRC_CR_RESET_Msk
5315
5316/******************************************************************************/
5317/* */
5318/* Digital Filter for Sigma Delta Modulators */
5319/* */
5320/******************************************************************************/
5321
5322/**************** DFSDM channel configuration registers ********************/
5323
5324/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
5325#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
5326#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
5327#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
5328#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
5329#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
5330#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
5331#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
5332#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
5333#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
5334#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
5335#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
5336#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
5337#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
5338#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
5339#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
5340#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
5341#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
5342#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
5343#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
5344#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
5345#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
5346#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
5347#define DFSDM_CHCFGR1_CHEN_Pos (7U)
5348#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
5349#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
5350#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
5351#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
5352#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
5353#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
5354#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
5355#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
5356#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
5357#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5358#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
5359#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5360#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5361#define DFSDM_CHCFGR1_SITP_Pos (0U)
5362#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
5363#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
5364#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
5365#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
5366
5367/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
5368#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
5369#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
5370#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
5371#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
5372#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
5373#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
5374
5375/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
5376#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
5377#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5378#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
5379#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5380#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5381#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
5382#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
5383#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
5384#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
5385#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
5386#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
5387#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
5388#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
5389#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
5390
5391/**************** Bit definition for DFSDM_CHWDATR register *******************/
5392#define DFSDM_CHWDATR_WDATA_Pos (0U)
5393#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
5394#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
5395
5396/**************** Bit definition for DFSDM_CHDATINR register *****************/
5397#define DFSDM_CHDATINR_INDAT0_Pos (0U)
5398#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
5399#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
5400#define DFSDM_CHDATINR_INDAT1_Pos (16U)
5401#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
5402#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
5403
5404/************************ DFSDM module registers ****************************/
5405
5406/***************** Bit definition for DFSDM_FLTCR1 register *******************/
5407#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
5408#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
5409#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
5410#define DFSDM_FLTCR1_FAST_Pos (29U)
5411#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
5412#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
5413#define DFSDM_FLTCR1_RCH_Pos (24U)
5414#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
5415#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
5416#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
5417#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
5418#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
5419#define DFSDM_FLTCR1_RSYNC_Pos (19U)
5420#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
5421#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
5422#define DFSDM_FLTCR1_RCONT_Pos (18U)
5423#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
5424#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
5425#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
5426#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
5427#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
5428#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
5429#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
5430#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
5431#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
5432#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
5433#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
5434#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5435#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
5436#define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5437#define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5438#define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5439#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
5440#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
5441#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
5442#define DFSDM_FLTCR1_JSCAN_Pos (4U)
5443#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
5444#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
5445#define DFSDM_FLTCR1_JSYNC_Pos (3U)
5446#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
5447#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
5448#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
5449#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
5450#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
5451#define DFSDM_FLTCR1_DFEN_Pos (0U)
5452#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
5453#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
5454
5455/***************** Bit definition for DFSDM_FLTCR2 register *******************/
5456#define DFSDM_FLTCR2_AWDCH_Pos (16U)
5457#define DFSDM_FLTCR2_AWDCH_Msk (0xFUL << DFSDM_FLTCR2_AWDCH_Pos)
5458#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
5459#define DFSDM_FLTCR2_EXCH_Pos (8U)
5460#define DFSDM_FLTCR2_EXCH_Msk (0xFUL << DFSDM_FLTCR2_EXCH_Pos)
5461#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
5462#define DFSDM_FLTCR2_CKABIE_Pos (6U)
5463#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
5464#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
5465#define DFSDM_FLTCR2_SCDIE_Pos (5U)
5466#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
5467#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
5468#define DFSDM_FLTCR2_AWDIE_Pos (4U)
5469#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
5470#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
5471#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
5472#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
5473#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
5474#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
5475#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
5476#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
5477#define DFSDM_FLTCR2_REOCIE_Pos (1U)
5478#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
5479#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
5480#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
5481#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
5482#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
5483
5484/***************** Bit definition for DFSDM_FLTISR register *******************/
5485#define DFSDM_FLTISR_SCDF_Pos (24U)
5486#define DFSDM_FLTISR_SCDF_Msk (0xFUL << DFSDM_FLTISR_SCDF_Pos)
5487#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
5488#define DFSDM_FLTISR_CKABF_Pos (16U)
5489#define DFSDM_FLTISR_CKABF_Msk (0xFUL << DFSDM_FLTISR_CKABF_Pos)
5490#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
5491#define DFSDM_FLTISR_RCIP_Pos (14U)
5492#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
5493#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
5494#define DFSDM_FLTISR_JCIP_Pos (13U)
5495#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
5496#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
5497#define DFSDM_FLTISR_AWDF_Pos (4U)
5498#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
5499#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
5500#define DFSDM_FLTISR_ROVRF_Pos (3U)
5501#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
5502#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
5503#define DFSDM_FLTISR_JOVRF_Pos (2U)
5504#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
5505#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
5506#define DFSDM_FLTISR_REOCF_Pos (1U)
5507#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
5508#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
5509#define DFSDM_FLTISR_JEOCF_Pos (0U)
5510#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
5511#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
5512
5513/***************** Bit definition for DFSDM_FLTICR register *******************/
5514#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
5515#define DFSDM_FLTICR_CLRSCDF_Msk (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos)
5516#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
5517#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
5518#define DFSDM_FLTICR_CLRCKABF_Msk (0xFUL << DFSDM_FLTICR_CLRCKABF_Pos)
5519#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
5520#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
5521#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
5522#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
5523#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
5524#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
5525#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
5526
5527/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
5528#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
5529#define DFSDM_FLTJCHGR_JCHG_Msk (0xFUL << DFSDM_FLTJCHGR_JCHG_Pos)
5530#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
5531/***************** Bit definition for DFSDM_FLTFCR register *******************/
5532#define DFSDM_FLTFCR_FORD_Pos (29U)
5533#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
5534#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
5535#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
5536#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
5537#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
5538#define DFSDM_FLTFCR_FOSR_Pos (16U)
5539#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
5540#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
5541#define DFSDM_FLTFCR_IOSR_Pos (0U)
5542#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
5543#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
5544
5545/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
5546#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
5547#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
5548#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
5549#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
5550#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
5551#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
5552
5553/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
5554#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
5555#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
5556#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
5557#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
5558#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
5559#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
5560#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
5561#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
5562#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
5563
5564/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
5565#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
5566#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
5567#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
5568#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
5569#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
5570#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
5571
5572/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
5573#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
5574#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
5575#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
5576#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
5577#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
5578#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
5579
5580/*************** Bit definition for DFSDM_FLTAWSR register *******************/
5581#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
5582#define DFSDM_FLTAWSR_AWHTF_Msk (0xFUL << DFSDM_FLTAWSR_AWHTF_Pos)
5583#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
5584#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
5585#define DFSDM_FLTAWSR_AWLTF_Msk (0xFUL << DFSDM_FLTAWSR_AWLTF_Pos)
5586#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
5587
5588/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
5589#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
5590#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
5591#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
5592#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
5593#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
5594#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
5595
5596/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
5597#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
5598#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
5599#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
5600#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
5601#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
5602#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
5603
5604/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
5605#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
5606#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
5607#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
5608#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
5609#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
5610#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
5611
5612/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
5613#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
5614#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
5615#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
5616
5617/* Legacy Defines */
5618#define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5619#define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
5620#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
5621
5622/******************************************************************************/
5623/* */
5624/* DMA Controller */
5625/* */
5626/******************************************************************************/
5627/******************** Bits definition for DMA_SxCR register *****************/
5628#define DMA_SxCR_CHSEL_Pos (25U)
5629#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5630#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5631#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
5632#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
5633#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
5634#define DMA_SxCR_MBURST_Pos (23U)
5635#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5636#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5637#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5638#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5639#define DMA_SxCR_PBURST_Pos (21U)
5640#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5641#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5642#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5643#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5644#define DMA_SxCR_CT_Pos (19U)
5645#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5646#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5647#define DMA_SxCR_DBM_Pos (18U)
5648#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5649#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5650#define DMA_SxCR_PL_Pos (16U)
5651#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5652#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5653#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5654#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5655#define DMA_SxCR_PINCOS_Pos (15U)
5656#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5657#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5658#define DMA_SxCR_MSIZE_Pos (13U)
5659#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5660#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5661#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5662#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5663#define DMA_SxCR_PSIZE_Pos (11U)
5664#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5665#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5666#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5667#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5668#define DMA_SxCR_MINC_Pos (10U)
5669#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5670#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5671#define DMA_SxCR_PINC_Pos (9U)
5672#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5673#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5674#define DMA_SxCR_CIRC_Pos (8U)
5675#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5676#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5677#define DMA_SxCR_DIR_Pos (6U)
5678#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5679#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5680#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5681#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5682#define DMA_SxCR_PFCTRL_Pos (5U)
5683#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5684#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5685#define DMA_SxCR_TCIE_Pos (4U)
5686#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5687#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5688#define DMA_SxCR_HTIE_Pos (3U)
5689#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5690#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5691#define DMA_SxCR_TEIE_Pos (2U)
5692#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5693#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5694#define DMA_SxCR_DMEIE_Pos (1U)
5695#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5696#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5697#define DMA_SxCR_EN_Pos (0U)
5698#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
5699#define DMA_SxCR_EN DMA_SxCR_EN_Msk
5700
5701/* Legacy defines */
5702#define DMA_SxCR_ACK_Pos (20U)
5703#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
5704#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5705
5706/******************** Bits definition for DMA_SxCNDTR register **************/
5707#define DMA_SxNDT_Pos (0U)
5708#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
5709#define DMA_SxNDT DMA_SxNDT_Msk
5710#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
5711#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
5712#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
5713#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
5714#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
5715#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
5716#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
5717#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
5718#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
5719#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
5720#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
5721#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
5722#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
5723#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
5724#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
5725#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
5726
5727/******************** Bits definition for DMA_SxFCR register ****************/
5728#define DMA_SxFCR_FEIE_Pos (7U)
5729#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
5730#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5731#define DMA_SxFCR_FS_Pos (3U)
5732#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
5733#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5734#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
5735#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
5736#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
5737#define DMA_SxFCR_DMDIS_Pos (2U)
5738#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
5739#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5740#define DMA_SxFCR_FTH_Pos (0U)
5741#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
5742#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5743#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
5744#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
5745
5746/******************** Bits definition for DMA_LISR register *****************/
5747#define DMA_LISR_TCIF3_Pos (27U)
5748#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
5749#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5750#define DMA_LISR_HTIF3_Pos (26U)
5751#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
5752#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5753#define DMA_LISR_TEIF3_Pos (25U)
5754#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
5755#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5756#define DMA_LISR_DMEIF3_Pos (24U)
5757#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
5758#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5759#define DMA_LISR_FEIF3_Pos (22U)
5760#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
5761#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5762#define DMA_LISR_TCIF2_Pos (21U)
5763#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
5764#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5765#define DMA_LISR_HTIF2_Pos (20U)
5766#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
5767#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5768#define DMA_LISR_TEIF2_Pos (19U)
5769#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
5770#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5771#define DMA_LISR_DMEIF2_Pos (18U)
5772#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
5773#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5774#define DMA_LISR_FEIF2_Pos (16U)
5775#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
5776#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5777#define DMA_LISR_TCIF1_Pos (11U)
5778#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
5779#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5780#define DMA_LISR_HTIF1_Pos (10U)
5781#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
5782#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5783#define DMA_LISR_TEIF1_Pos (9U)
5784#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
5785#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5786#define DMA_LISR_DMEIF1_Pos (8U)
5787#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
5788#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5789#define DMA_LISR_FEIF1_Pos (6U)
5790#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
5791#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5792#define DMA_LISR_TCIF0_Pos (5U)
5793#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
5794#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5795#define DMA_LISR_HTIF0_Pos (4U)
5796#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
5797#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5798#define DMA_LISR_TEIF0_Pos (3U)
5799#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
5800#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5801#define DMA_LISR_DMEIF0_Pos (2U)
5802#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
5803#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5804#define DMA_LISR_FEIF0_Pos (0U)
5805#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
5806#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5807
5808/******************** Bits definition for DMA_HISR register *****************/
5809#define DMA_HISR_TCIF7_Pos (27U)
5810#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
5811#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5812#define DMA_HISR_HTIF7_Pos (26U)
5813#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
5814#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
5815#define DMA_HISR_TEIF7_Pos (25U)
5816#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
5817#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
5818#define DMA_HISR_DMEIF7_Pos (24U)
5819#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
5820#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
5821#define DMA_HISR_FEIF7_Pos (22U)
5822#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
5823#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
5824#define DMA_HISR_TCIF6_Pos (21U)
5825#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
5826#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
5827#define DMA_HISR_HTIF6_Pos (20U)
5828#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
5829#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
5830#define DMA_HISR_TEIF6_Pos (19U)
5831#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
5832#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
5833#define DMA_HISR_DMEIF6_Pos (18U)
5834#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
5835#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
5836#define DMA_HISR_FEIF6_Pos (16U)
5837#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
5838#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
5839#define DMA_HISR_TCIF5_Pos (11U)
5840#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
5841#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
5842#define DMA_HISR_HTIF5_Pos (10U)
5843#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
5844#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
5845#define DMA_HISR_TEIF5_Pos (9U)
5846#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
5847#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
5848#define DMA_HISR_DMEIF5_Pos (8U)
5849#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
5850#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
5851#define DMA_HISR_FEIF5_Pos (6U)
5852#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
5853#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
5854#define DMA_HISR_TCIF4_Pos (5U)
5855#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
5856#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
5857#define DMA_HISR_HTIF4_Pos (4U)
5858#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
5859#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
5860#define DMA_HISR_TEIF4_Pos (3U)
5861#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
5862#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
5863#define DMA_HISR_DMEIF4_Pos (2U)
5864#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
5865#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
5866#define DMA_HISR_FEIF4_Pos (0U)
5867#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
5868#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
5869
5870/******************** Bits definition for DMA_LIFCR register ****************/
5871#define DMA_LIFCR_CTCIF3_Pos (27U)
5872#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
5873#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
5874#define DMA_LIFCR_CHTIF3_Pos (26U)
5875#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
5876#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
5877#define DMA_LIFCR_CTEIF3_Pos (25U)
5878#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
5879#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
5880#define DMA_LIFCR_CDMEIF3_Pos (24U)
5881#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
5882#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
5883#define DMA_LIFCR_CFEIF3_Pos (22U)
5884#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
5885#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
5886#define DMA_LIFCR_CTCIF2_Pos (21U)
5887#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
5888#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
5889#define DMA_LIFCR_CHTIF2_Pos (20U)
5890#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
5891#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
5892#define DMA_LIFCR_CTEIF2_Pos (19U)
5893#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
5894#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
5895#define DMA_LIFCR_CDMEIF2_Pos (18U)
5896#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
5897#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
5898#define DMA_LIFCR_CFEIF2_Pos (16U)
5899#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
5900#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
5901#define DMA_LIFCR_CTCIF1_Pos (11U)
5902#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
5903#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
5904#define DMA_LIFCR_CHTIF1_Pos (10U)
5905#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
5906#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
5907#define DMA_LIFCR_CTEIF1_Pos (9U)
5908#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
5909#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
5910#define DMA_LIFCR_CDMEIF1_Pos (8U)
5911#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
5912#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
5913#define DMA_LIFCR_CFEIF1_Pos (6U)
5914#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
5915#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
5916#define DMA_LIFCR_CTCIF0_Pos (5U)
5917#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
5918#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
5919#define DMA_LIFCR_CHTIF0_Pos (4U)
5920#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
5921#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
5922#define DMA_LIFCR_CTEIF0_Pos (3U)
5923#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
5924#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
5925#define DMA_LIFCR_CDMEIF0_Pos (2U)
5926#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
5927#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
5928#define DMA_LIFCR_CFEIF0_Pos (0U)
5929#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
5930#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
5931
5932/******************** Bits definition for DMA_HIFCR register ****************/
5933#define DMA_HIFCR_CTCIF7_Pos (27U)
5934#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
5935#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
5936#define DMA_HIFCR_CHTIF7_Pos (26U)
5937#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
5938#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
5939#define DMA_HIFCR_CTEIF7_Pos (25U)
5940#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
5941#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
5942#define DMA_HIFCR_CDMEIF7_Pos (24U)
5943#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
5944#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
5945#define DMA_HIFCR_CFEIF7_Pos (22U)
5946#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
5947#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
5948#define DMA_HIFCR_CTCIF6_Pos (21U)
5949#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
5950#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
5951#define DMA_HIFCR_CHTIF6_Pos (20U)
5952#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
5953#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
5954#define DMA_HIFCR_CTEIF6_Pos (19U)
5955#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
5956#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
5957#define DMA_HIFCR_CDMEIF6_Pos (18U)
5958#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
5959#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
5960#define DMA_HIFCR_CFEIF6_Pos (16U)
5961#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
5962#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
5963#define DMA_HIFCR_CTCIF5_Pos (11U)
5964#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
5965#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
5966#define DMA_HIFCR_CHTIF5_Pos (10U)
5967#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
5968#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
5969#define DMA_HIFCR_CTEIF5_Pos (9U)
5970#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
5971#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
5972#define DMA_HIFCR_CDMEIF5_Pos (8U)
5973#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
5974#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
5975#define DMA_HIFCR_CFEIF5_Pos (6U)
5976#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
5977#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
5978#define DMA_HIFCR_CTCIF4_Pos (5U)
5979#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
5980#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
5981#define DMA_HIFCR_CHTIF4_Pos (4U)
5982#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
5983#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
5984#define DMA_HIFCR_CTEIF4_Pos (3U)
5985#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
5986#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
5987#define DMA_HIFCR_CDMEIF4_Pos (2U)
5988#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
5989#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
5990#define DMA_HIFCR_CFEIF4_Pos (0U)
5991#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
5992#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
5993
5994/****************** Bit definition for DMA_SxPAR register ********************/
5995#define DMA_SxPAR_PA_Pos (0U)
5996#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
5997#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
5998
5999/****************** Bit definition for DMA_SxM0AR register ********************/
6000#define DMA_SxM0AR_M0A_Pos (0U)
6001#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6002#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6003
6004/****************** Bit definition for DMA_SxM1AR register ********************/
6005#define DMA_SxM1AR_M1A_Pos (0U)
6006#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6007#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6008
6009
6010/******************************************************************************/
6011/* */
6012/* External Interrupt/Event Controller */
6013/* */
6014/******************************************************************************/
6015/******************* Bit definition for EXTI_IMR register *******************/
6016#define EXTI_IMR_MR0_Pos (0U)
6017#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6018#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6019#define EXTI_IMR_MR1_Pos (1U)
6020#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6021#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6022#define EXTI_IMR_MR2_Pos (2U)
6023#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6024#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6025#define EXTI_IMR_MR3_Pos (3U)
6026#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6027#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6028#define EXTI_IMR_MR4_Pos (4U)
6029#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6030#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6031#define EXTI_IMR_MR5_Pos (5U)
6032#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6033#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6034#define EXTI_IMR_MR6_Pos (6U)
6035#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6036#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6037#define EXTI_IMR_MR7_Pos (7U)
6038#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6039#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6040#define EXTI_IMR_MR8_Pos (8U)
6041#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6042#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6043#define EXTI_IMR_MR9_Pos (9U)
6044#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6045#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6046#define EXTI_IMR_MR10_Pos (10U)
6047#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6048#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6049#define EXTI_IMR_MR11_Pos (11U)
6050#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6051#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6052#define EXTI_IMR_MR12_Pos (12U)
6053#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6054#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6055#define EXTI_IMR_MR13_Pos (13U)
6056#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6057#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6058#define EXTI_IMR_MR14_Pos (14U)
6059#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6060#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6061#define EXTI_IMR_MR15_Pos (15U)
6062#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6063#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6064#define EXTI_IMR_MR16_Pos (16U)
6065#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6066#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6067#define EXTI_IMR_MR17_Pos (17U)
6068#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6069#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6070#define EXTI_IMR_MR18_Pos (18U)
6071#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6072#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6073#define EXTI_IMR_MR19_Pos (19U)
6074#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6075#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6076#define EXTI_IMR_MR20_Pos (20U)
6077#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6078#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6079#define EXTI_IMR_MR21_Pos (21U)
6080#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6081#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6082#define EXTI_IMR_MR22_Pos (22U)
6083#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6084#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6085
6086/* Reference Defines */
6087#define EXTI_IMR_IM0 EXTI_IMR_MR0
6088#define EXTI_IMR_IM1 EXTI_IMR_MR1
6089#define EXTI_IMR_IM2 EXTI_IMR_MR2
6090#define EXTI_IMR_IM3 EXTI_IMR_MR3
6091#define EXTI_IMR_IM4 EXTI_IMR_MR4
6092#define EXTI_IMR_IM5 EXTI_IMR_MR5
6093#define EXTI_IMR_IM6 EXTI_IMR_MR6
6094#define EXTI_IMR_IM7 EXTI_IMR_MR7
6095#define EXTI_IMR_IM8 EXTI_IMR_MR8
6096#define EXTI_IMR_IM9 EXTI_IMR_MR9
6097#define EXTI_IMR_IM10 EXTI_IMR_MR10
6098#define EXTI_IMR_IM11 EXTI_IMR_MR11
6099#define EXTI_IMR_IM12 EXTI_IMR_MR12
6100#define EXTI_IMR_IM13 EXTI_IMR_MR13
6101#define EXTI_IMR_IM14 EXTI_IMR_MR14
6102#define EXTI_IMR_IM15 EXTI_IMR_MR15
6103#define EXTI_IMR_IM16 EXTI_IMR_MR16
6104#define EXTI_IMR_IM17 EXTI_IMR_MR17
6105#define EXTI_IMR_IM18 EXTI_IMR_MR18
6106#define EXTI_IMR_IM19 EXTI_IMR_MR19
6107#define EXTI_IMR_IM20 EXTI_IMR_MR20
6108#define EXTI_IMR_IM21 EXTI_IMR_MR21
6109#define EXTI_IMR_IM22 EXTI_IMR_MR22
6110#define EXTI_IMR_IM_Pos (0U)
6111#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6112#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6113
6114/******************* Bit definition for EXTI_EMR register *******************/
6115#define EXTI_EMR_MR0_Pos (0U)
6116#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6117#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6118#define EXTI_EMR_MR1_Pos (1U)
6119#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6120#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6121#define EXTI_EMR_MR2_Pos (2U)
6122#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6123#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6124#define EXTI_EMR_MR3_Pos (3U)
6125#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6126#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6127#define EXTI_EMR_MR4_Pos (4U)
6128#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6129#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6130#define EXTI_EMR_MR5_Pos (5U)
6131#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6132#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6133#define EXTI_EMR_MR6_Pos (6U)
6134#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6135#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6136#define EXTI_EMR_MR7_Pos (7U)
6137#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6138#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6139#define EXTI_EMR_MR8_Pos (8U)
6140#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6141#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6142#define EXTI_EMR_MR9_Pos (9U)
6143#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6144#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6145#define EXTI_EMR_MR10_Pos (10U)
6146#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6147#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6148#define EXTI_EMR_MR11_Pos (11U)
6149#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6150#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6151#define EXTI_EMR_MR12_Pos (12U)
6152#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6153#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6154#define EXTI_EMR_MR13_Pos (13U)
6155#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6156#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6157#define EXTI_EMR_MR14_Pos (14U)
6158#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6159#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6160#define EXTI_EMR_MR15_Pos (15U)
6161#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6162#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6163#define EXTI_EMR_MR16_Pos (16U)
6164#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6165#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6166#define EXTI_EMR_MR17_Pos (17U)
6167#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6168#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6169#define EXTI_EMR_MR18_Pos (18U)
6170#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6171#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6172#define EXTI_EMR_MR19_Pos (19U)
6173#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6174#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6175#define EXTI_EMR_MR20_Pos (20U)
6176#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6177#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6178#define EXTI_EMR_MR21_Pos (21U)
6179#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6180#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6181#define EXTI_EMR_MR22_Pos (22U)
6182#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6183#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6184
6185/* Reference Defines */
6186#define EXTI_EMR_EM0 EXTI_EMR_MR0
6187#define EXTI_EMR_EM1 EXTI_EMR_MR1
6188#define EXTI_EMR_EM2 EXTI_EMR_MR2
6189#define EXTI_EMR_EM3 EXTI_EMR_MR3
6190#define EXTI_EMR_EM4 EXTI_EMR_MR4
6191#define EXTI_EMR_EM5 EXTI_EMR_MR5
6192#define EXTI_EMR_EM6 EXTI_EMR_MR6
6193#define EXTI_EMR_EM7 EXTI_EMR_MR7
6194#define EXTI_EMR_EM8 EXTI_EMR_MR8
6195#define EXTI_EMR_EM9 EXTI_EMR_MR9
6196#define EXTI_EMR_EM10 EXTI_EMR_MR10
6197#define EXTI_EMR_EM11 EXTI_EMR_MR11
6198#define EXTI_EMR_EM12 EXTI_EMR_MR12
6199#define EXTI_EMR_EM13 EXTI_EMR_MR13
6200#define EXTI_EMR_EM14 EXTI_EMR_MR14
6201#define EXTI_EMR_EM15 EXTI_EMR_MR15
6202#define EXTI_EMR_EM16 EXTI_EMR_MR16
6203#define EXTI_EMR_EM17 EXTI_EMR_MR17
6204#define EXTI_EMR_EM18 EXTI_EMR_MR18
6205#define EXTI_EMR_EM19 EXTI_EMR_MR19
6206#define EXTI_EMR_EM20 EXTI_EMR_MR20
6207#define EXTI_EMR_EM21 EXTI_EMR_MR21
6208#define EXTI_EMR_EM22 EXTI_EMR_MR22
6209
6210/****************** Bit definition for EXTI_RTSR register *******************/
6211#define EXTI_RTSR_TR0_Pos (0U)
6212#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6213#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6214#define EXTI_RTSR_TR1_Pos (1U)
6215#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6216#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6217#define EXTI_RTSR_TR2_Pos (2U)
6218#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6219#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6220#define EXTI_RTSR_TR3_Pos (3U)
6221#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6222#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6223#define EXTI_RTSR_TR4_Pos (4U)
6224#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6225#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6226#define EXTI_RTSR_TR5_Pos (5U)
6227#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6228#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6229#define EXTI_RTSR_TR6_Pos (6U)
6230#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6231#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6232#define EXTI_RTSR_TR7_Pos (7U)
6233#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6234#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6235#define EXTI_RTSR_TR8_Pos (8U)
6236#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6237#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6238#define EXTI_RTSR_TR9_Pos (9U)
6239#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6240#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6241#define EXTI_RTSR_TR10_Pos (10U)
6242#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6243#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6244#define EXTI_RTSR_TR11_Pos (11U)
6245#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6246#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6247#define EXTI_RTSR_TR12_Pos (12U)
6248#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6249#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6250#define EXTI_RTSR_TR13_Pos (13U)
6251#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6252#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6253#define EXTI_RTSR_TR14_Pos (14U)
6254#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6255#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6256#define EXTI_RTSR_TR15_Pos (15U)
6257#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6258#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6259#define EXTI_RTSR_TR16_Pos (16U)
6260#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6261#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6262#define EXTI_RTSR_TR17_Pos (17U)
6263#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6264#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6265#define EXTI_RTSR_TR18_Pos (18U)
6266#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6267#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6268#define EXTI_RTSR_TR19_Pos (19U)
6269#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6270#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6271#define EXTI_RTSR_TR20_Pos (20U)
6272#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6273#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6274#define EXTI_RTSR_TR21_Pos (21U)
6275#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6276#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6277#define EXTI_RTSR_TR22_Pos (22U)
6278#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6279#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6280
6281/****************** Bit definition for EXTI_FTSR register *******************/
6282#define EXTI_FTSR_TR0_Pos (0U)
6283#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6284#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6285#define EXTI_FTSR_TR1_Pos (1U)
6286#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6287#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6288#define EXTI_FTSR_TR2_Pos (2U)
6289#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6290#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6291#define EXTI_FTSR_TR3_Pos (3U)
6292#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6293#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6294#define EXTI_FTSR_TR4_Pos (4U)
6295#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6296#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6297#define EXTI_FTSR_TR5_Pos (5U)
6298#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6299#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6300#define EXTI_FTSR_TR6_Pos (6U)
6301#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6302#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6303#define EXTI_FTSR_TR7_Pos (7U)
6304#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6305#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6306#define EXTI_FTSR_TR8_Pos (8U)
6307#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6308#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6309#define EXTI_FTSR_TR9_Pos (9U)
6310#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6311#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6312#define EXTI_FTSR_TR10_Pos (10U)
6313#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6314#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6315#define EXTI_FTSR_TR11_Pos (11U)
6316#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6317#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6318#define EXTI_FTSR_TR12_Pos (12U)
6319#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6320#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6321#define EXTI_FTSR_TR13_Pos (13U)
6322#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6323#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6324#define EXTI_FTSR_TR14_Pos (14U)
6325#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6326#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6327#define EXTI_FTSR_TR15_Pos (15U)
6328#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6329#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6330#define EXTI_FTSR_TR16_Pos (16U)
6331#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6332#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6333#define EXTI_FTSR_TR17_Pos (17U)
6334#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6335#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6336#define EXTI_FTSR_TR18_Pos (18U)
6337#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6338#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6339#define EXTI_FTSR_TR19_Pos (19U)
6340#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6341#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6342#define EXTI_FTSR_TR20_Pos (20U)
6343#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6344#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6345#define EXTI_FTSR_TR21_Pos (21U)
6346#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6347#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6348#define EXTI_FTSR_TR22_Pos (22U)
6349#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6350#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6351
6352/****************** Bit definition for EXTI_SWIER register ******************/
6353#define EXTI_SWIER_SWIER0_Pos (0U)
6354#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6355#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6356#define EXTI_SWIER_SWIER1_Pos (1U)
6357#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6358#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6359#define EXTI_SWIER_SWIER2_Pos (2U)
6360#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6361#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6362#define EXTI_SWIER_SWIER3_Pos (3U)
6363#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6364#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6365#define EXTI_SWIER_SWIER4_Pos (4U)
6366#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6367#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6368#define EXTI_SWIER_SWIER5_Pos (5U)
6369#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6370#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6371#define EXTI_SWIER_SWIER6_Pos (6U)
6372#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6373#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6374#define EXTI_SWIER_SWIER7_Pos (7U)
6375#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6376#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6377#define EXTI_SWIER_SWIER8_Pos (8U)
6378#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6379#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6380#define EXTI_SWIER_SWIER9_Pos (9U)
6381#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6382#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6383#define EXTI_SWIER_SWIER10_Pos (10U)
6384#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6385#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6386#define EXTI_SWIER_SWIER11_Pos (11U)
6387#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6388#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6389#define EXTI_SWIER_SWIER12_Pos (12U)
6390#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6391#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6392#define EXTI_SWIER_SWIER13_Pos (13U)
6393#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6394#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6395#define EXTI_SWIER_SWIER14_Pos (14U)
6396#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6397#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6398#define EXTI_SWIER_SWIER15_Pos (15U)
6399#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6400#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6401#define EXTI_SWIER_SWIER16_Pos (16U)
6402#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6403#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6404#define EXTI_SWIER_SWIER17_Pos (17U)
6405#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6406#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6407#define EXTI_SWIER_SWIER18_Pos (18U)
6408#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6409#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6410#define EXTI_SWIER_SWIER19_Pos (19U)
6411#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6412#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6413#define EXTI_SWIER_SWIER20_Pos (20U)
6414#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6415#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6416#define EXTI_SWIER_SWIER21_Pos (21U)
6417#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6418#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6419#define EXTI_SWIER_SWIER22_Pos (22U)
6420#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6421#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6422
6423/******************* Bit definition for EXTI_PR register ********************/
6424#define EXTI_PR_PR0_Pos (0U)
6425#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6426#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6427#define EXTI_PR_PR1_Pos (1U)
6428#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6429#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6430#define EXTI_PR_PR2_Pos (2U)
6431#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6432#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6433#define EXTI_PR_PR3_Pos (3U)
6434#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6435#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6436#define EXTI_PR_PR4_Pos (4U)
6437#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6438#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6439#define EXTI_PR_PR5_Pos (5U)
6440#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6441#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6442#define EXTI_PR_PR6_Pos (6U)
6443#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6444#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6445#define EXTI_PR_PR7_Pos (7U)
6446#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6447#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6448#define EXTI_PR_PR8_Pos (8U)
6449#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6450#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6451#define EXTI_PR_PR9_Pos (9U)
6452#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6453#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6454#define EXTI_PR_PR10_Pos (10U)
6455#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6456#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6457#define EXTI_PR_PR11_Pos (11U)
6458#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6459#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6460#define EXTI_PR_PR12_Pos (12U)
6461#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6462#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6463#define EXTI_PR_PR13_Pos (13U)
6464#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6465#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6466#define EXTI_PR_PR14_Pos (14U)
6467#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6468#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6469#define EXTI_PR_PR15_Pos (15U)
6470#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6471#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6472#define EXTI_PR_PR16_Pos (16U)
6473#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6474#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6475#define EXTI_PR_PR17_Pos (17U)
6476#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6477#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6478#define EXTI_PR_PR18_Pos (18U)
6479#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6480#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6481#define EXTI_PR_PR19_Pos (19U)
6482#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6483#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6484#define EXTI_PR_PR20_Pos (20U)
6485#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6486#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6487#define EXTI_PR_PR21_Pos (21U)
6488#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6489#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6490#define EXTI_PR_PR22_Pos (22U)
6491#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6492#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6493
6494/******************************************************************************/
6495/* */
6496/* FLASH */
6497/* */
6498/******************************************************************************/
6499/******************* Bits definition for FLASH_ACR register *****************/
6500#define FLASH_ACR_LATENCY_Pos (0U)
6501#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6502#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6503#define FLASH_ACR_LATENCY_0WS 0x00000000U
6504#define FLASH_ACR_LATENCY_1WS 0x00000001U
6505#define FLASH_ACR_LATENCY_2WS 0x00000002U
6506#define FLASH_ACR_LATENCY_3WS 0x00000003U
6507#define FLASH_ACR_LATENCY_4WS 0x00000004U
6508#define FLASH_ACR_LATENCY_5WS 0x00000005U
6509#define FLASH_ACR_LATENCY_6WS 0x00000006U
6510#define FLASH_ACR_LATENCY_7WS 0x00000007U
6511
6512
6513#define FLASH_ACR_PRFTEN_Pos (8U)
6514#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6515#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6516#define FLASH_ACR_ICEN_Pos (9U)
6517#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6518#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6519#define FLASH_ACR_DCEN_Pos (10U)
6520#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6521#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6522#define FLASH_ACR_ICRST_Pos (11U)
6523#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6524#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6525#define FLASH_ACR_DCRST_Pos (12U)
6526#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6527#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6528
6529/******************* Bits definition for FLASH_SR register ******************/
6530#define FLASH_SR_EOP_Pos (0U)
6531#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6532#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6533#define FLASH_SR_OPERR_Pos (1U)
6534#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
6535#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
6536#define FLASH_SR_WRPERR_Pos (4U)
6537#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6538#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6539#define FLASH_SR_PGAERR_Pos (5U)
6540#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6541#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6542#define FLASH_SR_PGPERR_Pos (6U)
6543#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6544#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6545#define FLASH_SR_PGSERR_Pos (7U)
6546#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6547#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6548#define FLASH_SR_RDERR_Pos (8U)
6549#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
6550#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6551#define FLASH_SR_BSY_Pos (16U)
6552#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6553#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6554
6555/******************* Bits definition for FLASH_CR register ******************/
6556#define FLASH_CR_PG_Pos (0U)
6557#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6558#define FLASH_CR_PG FLASH_CR_PG_Msk
6559#define FLASH_CR_SER_Pos (1U)
6560#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6561#define FLASH_CR_SER FLASH_CR_SER_Msk
6562#define FLASH_CR_MER_Pos (2U)
6563#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6564#define FLASH_CR_MER FLASH_CR_MER_Msk
6565#define FLASH_CR_SNB_Pos (3U)
6566#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
6567#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6568#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6569#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6570#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6571#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6572#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
6573#define FLASH_CR_PSIZE_Pos (8U)
6574#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6575#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6576#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6577#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6578#define FLASH_CR_STRT_Pos (16U)
6579#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6580#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6581#define FLASH_CR_EOPIE_Pos (24U)
6582#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6583#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6584#define FLASH_CR_ERRIE_Pos (25U)
6585#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6586#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6587#define FLASH_CR_LOCK_Pos (31U)
6588#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6589#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6590
6591/******************* Bits definition for FLASH_OPTCR register ***************/
6592#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6593#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6594#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6595#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6596#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6597#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6598
6599#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6600#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6601#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6602#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6603#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6604#define FLASH_OPTCR_WDG_SW_Pos (5U)
6605#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6606#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6607#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6608#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6609#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6610#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6611#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6612#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6613#define FLASH_OPTCR_RDP_Pos (8U)
6614#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6615#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6616#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6617#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6618#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6619#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6620#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6621#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6622#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6623#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6624#define FLASH_OPTCR_nWRP_Pos (16U)
6625#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
6626#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6627#define FLASH_OPTCR_nWRP_0 0x00010000U
6628#define FLASH_OPTCR_nWRP_1 0x00020000U
6629#define FLASH_OPTCR_nWRP_2 0x00040000U
6630#define FLASH_OPTCR_nWRP_3 0x00080000U
6631#define FLASH_OPTCR_nWRP_4 0x00100000U
6632#define FLASH_OPTCR_nWRP_5 0x00200000U
6633#define FLASH_OPTCR_nWRP_6 0x00400000U
6634#define FLASH_OPTCR_nWRP_7 0x00800000U
6635#define FLASH_OPTCR_nWRP_8 0x01000000U
6636#define FLASH_OPTCR_nWRP_9 0x02000000U
6637#define FLASH_OPTCR_nWRP_10 0x04000000U
6638#define FLASH_OPTCR_nWRP_11 0x08000000U
6639
6640/****************** Bits definition for FLASH_OPTCR1 register ***************/
6641#define FLASH_OPTCR1_nWRP_Pos (16U)
6642#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
6643#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6644#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
6645#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
6646#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
6647#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
6648#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
6649#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
6650#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
6651#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
6652#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
6653#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
6654#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
6655#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
6656/* Legacy defines */
6657#define FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
6658#define FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
6659#define FLASH_SR_SOP FLASH_SR_OPERR
6660#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6661#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6662#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6663#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6664#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6665#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6666
6667/******************************************************************************/
6668/* */
6669/* Flexible Static Memory Controller */
6670/* */
6671/******************************************************************************/
6672/****************** Bit definition for FSMC_BCR1 register *******************/
6673#define FSMC_BCR1_MBKEN_Pos (0U)
6674#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
6675#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
6676#define FSMC_BCR1_MUXEN_Pos (1U)
6677#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
6678#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
6679
6680#define FSMC_BCR1_MTYP_Pos (2U)
6681#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
6682#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
6683#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
6684#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
6685
6686#define FSMC_BCR1_MWID_Pos (4U)
6687#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
6688#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
6689#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
6690#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
6691
6692#define FSMC_BCR1_FACCEN_Pos (6U)
6693#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
6694#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
6695#define FSMC_BCR1_BURSTEN_Pos (8U)
6696#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
6697#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
6698#define FSMC_BCR1_WAITPOL_Pos (9U)
6699#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
6700#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
6701#define FSMC_BCR1_WAITCFG_Pos (11U)
6702#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
6703#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
6704#define FSMC_BCR1_WREN_Pos (12U)
6705#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
6706#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
6707#define FSMC_BCR1_WAITEN_Pos (13U)
6708#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
6709#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
6710#define FSMC_BCR1_EXTMOD_Pos (14U)
6711#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
6712#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
6713#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6714#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
6715#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
6716#define FSMC_BCR1_CPSIZE_Pos (16U)
6717#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
6718#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
6719#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
6720#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
6721#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
6722#define FSMC_BCR1_CBURSTRW_Pos (19U)
6723#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
6724#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
6725#define FSMC_BCR1_CCLKEN_Pos (20U)
6726#define FSMC_BCR1_CCLKEN_Msk (0x1UL << FSMC_BCR1_CCLKEN_Pos)
6727#define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk
6728#define FSMC_BCR1_WFDIS_Pos (21U)
6729#define FSMC_BCR1_WFDIS_Msk (0x1UL << FSMC_BCR1_WFDIS_Pos)
6730#define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk
6731
6732/****************** Bit definition for FSMC_BCR2 register *******************/
6733#define FSMC_BCR2_MBKEN_Pos (0U)
6734#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
6735#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
6736#define FSMC_BCR2_MUXEN_Pos (1U)
6737#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
6738#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
6739
6740#define FSMC_BCR2_MTYP_Pos (2U)
6741#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
6742#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
6743#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
6744#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
6745
6746#define FSMC_BCR2_MWID_Pos (4U)
6747#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
6748#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
6749#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
6750#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
6751
6752#define FSMC_BCR2_FACCEN_Pos (6U)
6753#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
6754#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
6755#define FSMC_BCR2_BURSTEN_Pos (8U)
6756#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
6757#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
6758#define FSMC_BCR2_WAITPOL_Pos (9U)
6759#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
6760#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
6761#define FSMC_BCR2_WAITCFG_Pos (11U)
6762#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
6763#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
6764#define FSMC_BCR2_WREN_Pos (12U)
6765#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
6766#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
6767#define FSMC_BCR2_WAITEN_Pos (13U)
6768#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
6769#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
6770#define FSMC_BCR2_EXTMOD_Pos (14U)
6771#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
6772#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
6773#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6774#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
6775#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
6776#define FSMC_BCR2_CPSIZE_Pos (16U)
6777#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
6778#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
6779#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
6780#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
6781#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
6782#define FSMC_BCR2_CBURSTRW_Pos (19U)
6783#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
6784#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
6785
6786/****************** Bit definition for FSMC_BCR3 register *******************/
6787#define FSMC_BCR3_MBKEN_Pos (0U)
6788#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
6789#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
6790#define FSMC_BCR3_MUXEN_Pos (1U)
6791#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
6792#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
6793
6794#define FSMC_BCR3_MTYP_Pos (2U)
6795#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
6796#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
6797#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
6798#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
6799
6800#define FSMC_BCR3_MWID_Pos (4U)
6801#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
6802#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
6803#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
6804#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
6805
6806#define FSMC_BCR3_FACCEN_Pos (6U)
6807#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
6808#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
6809#define FSMC_BCR3_BURSTEN_Pos (8U)
6810#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
6811#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
6812#define FSMC_BCR3_WAITPOL_Pos (9U)
6813#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
6814#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
6815#define FSMC_BCR3_WAITCFG_Pos (11U)
6816#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
6817#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
6818#define FSMC_BCR3_WREN_Pos (12U)
6819#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
6820#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
6821#define FSMC_BCR3_WAITEN_Pos (13U)
6822#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
6823#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
6824#define FSMC_BCR3_EXTMOD_Pos (14U)
6825#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
6826#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
6827#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
6828#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
6829#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
6830#define FSMC_BCR3_CPSIZE_Pos (16U)
6831#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
6832#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
6833#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
6834#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
6835#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
6836#define FSMC_BCR3_CBURSTRW_Pos (19U)
6837#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
6838#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
6839
6840/****************** Bit definition for FSMC_BCR4 register *******************/
6841#define FSMC_BCR4_MBKEN_Pos (0U)
6842#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
6843#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
6844#define FSMC_BCR4_MUXEN_Pos (1U)
6845#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
6846#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
6847
6848#define FSMC_BCR4_MTYP_Pos (2U)
6849#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
6850#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
6851#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
6852#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
6853
6854#define FSMC_BCR4_MWID_Pos (4U)
6855#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
6856#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
6857#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
6858#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
6859
6860#define FSMC_BCR4_FACCEN_Pos (6U)
6861#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
6862#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
6863#define FSMC_BCR4_BURSTEN_Pos (8U)
6864#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
6865#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
6866#define FSMC_BCR4_WAITPOL_Pos (9U)
6867#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
6868#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
6869#define FSMC_BCR4_WAITCFG_Pos (11U)
6870#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
6871#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
6872#define FSMC_BCR4_WREN_Pos (12U)
6873#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
6874#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
6875#define FSMC_BCR4_WAITEN_Pos (13U)
6876#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
6877#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
6878#define FSMC_BCR4_EXTMOD_Pos (14U)
6879#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
6880#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
6881#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
6882#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
6883#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
6884#define FSMC_BCR4_CPSIZE_Pos (16U)
6885#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
6886#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
6887#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
6888#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
6889#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
6890#define FSMC_BCR4_CBURSTRW_Pos (19U)
6891#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
6892#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
6893
6894/****************** Bit definition for FSMC_BTR1 register ******************/
6895#define FSMC_BTR1_ADDSET_Pos (0U)
6896#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
6897#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
6898#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
6899#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
6900#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
6901#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
6902
6903#define FSMC_BTR1_ADDHLD_Pos (4U)
6904#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
6905#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
6906#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
6907#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
6908#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
6909#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
6910
6911#define FSMC_BTR1_DATAST_Pos (8U)
6912#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
6913#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
6914#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
6915#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
6916#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
6917#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
6918#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
6919#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
6920#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
6921#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
6922
6923#define FSMC_BTR1_BUSTURN_Pos (16U)
6924#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
6925#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
6926#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
6927#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
6928#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
6929#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
6930
6931#define FSMC_BTR1_CLKDIV_Pos (20U)
6932#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
6933#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
6934#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
6935#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
6936#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
6937#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
6938
6939#define FSMC_BTR1_DATLAT_Pos (24U)
6940#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
6941#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
6942#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
6943#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
6944#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
6945#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
6946
6947#define FSMC_BTR1_ACCMOD_Pos (28U)
6948#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
6949#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
6950#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
6951#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
6952
6953/****************** Bit definition for FSMC_BTR2 register *******************/
6954#define FSMC_BTR2_ADDSET_Pos (0U)
6955#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
6956#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
6957#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
6958#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
6959#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
6960#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
6961
6962#define FSMC_BTR2_ADDHLD_Pos (4U)
6963#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
6964#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
6965#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
6966#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
6967#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
6968#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
6969
6970#define FSMC_BTR2_DATAST_Pos (8U)
6971#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
6972#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
6973#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
6974#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
6975#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
6976#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
6977#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
6978#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
6979#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
6980#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
6981
6982#define FSMC_BTR2_BUSTURN_Pos (16U)
6983#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
6984#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
6985#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
6986#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
6987#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
6988#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
6989
6990#define FSMC_BTR2_CLKDIV_Pos (20U)
6991#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
6992#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
6993#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
6994#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
6995#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
6996#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
6997
6998#define FSMC_BTR2_DATLAT_Pos (24U)
6999#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
7000#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
7001#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
7002#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
7003#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
7004#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
7005
7006#define FSMC_BTR2_ACCMOD_Pos (28U)
7007#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
7008#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
7009#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
7010#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
7011
7012/******************* Bit definition for FSMC_BTR3 register *******************/
7013#define FSMC_BTR3_ADDSET_Pos (0U)
7014#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
7015#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
7016#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
7017#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
7018#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
7019#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
7020
7021#define FSMC_BTR3_ADDHLD_Pos (4U)
7022#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
7023#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
7024#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
7025#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
7026#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
7027#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
7028
7029#define FSMC_BTR3_DATAST_Pos (8U)
7030#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
7031#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
7032#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
7033#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
7034#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
7035#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
7036#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
7037#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
7038#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
7039#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
7040
7041#define FSMC_BTR3_BUSTURN_Pos (16U)
7042#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
7043#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
7044#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
7045#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
7046#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
7047#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
7048
7049#define FSMC_BTR3_CLKDIV_Pos (20U)
7050#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
7051#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
7052#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
7053#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
7054#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
7055#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
7056
7057#define FSMC_BTR3_DATLAT_Pos (24U)
7058#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
7059#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
7060#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
7061#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
7062#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
7063#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
7064
7065#define FSMC_BTR3_ACCMOD_Pos (28U)
7066#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
7067#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
7068#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
7069#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
7070
7071/****************** Bit definition for FSMC_BTR4 register *******************/
7072#define FSMC_BTR4_ADDSET_Pos (0U)
7073#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
7074#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
7075#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
7076#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
7077#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
7078#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
7079
7080#define FSMC_BTR4_ADDHLD_Pos (4U)
7081#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
7082#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
7083#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
7084#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
7085#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
7086#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
7087
7088#define FSMC_BTR4_DATAST_Pos (8U)
7089#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
7090#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
7091#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
7092#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
7093#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
7094#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
7095#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
7096#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
7097#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
7098#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
7099
7100#define FSMC_BTR4_BUSTURN_Pos (16U)
7101#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
7102#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
7103#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
7104#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
7105#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
7106#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
7107
7108#define FSMC_BTR4_CLKDIV_Pos (20U)
7109#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
7110#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
7111#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
7112#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
7113#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
7114#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
7115
7116#define FSMC_BTR4_DATLAT_Pos (24U)
7117#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7118#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7119#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7120#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7121#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7122#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7123
7124#define FSMC_BTR4_ACCMOD_Pos (28U)
7125#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7126#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7127#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7128#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7129
7130/****************** Bit definition for FSMC_BWTR1 register ******************/
7131#define FSMC_BWTR1_ADDSET_Pos (0U)
7132#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7133#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7134#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7135#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7136#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7137#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7138
7139#define FSMC_BWTR1_ADDHLD_Pos (4U)
7140#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7141#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7142#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7143#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7144#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7145#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7146
7147#define FSMC_BWTR1_DATAST_Pos (8U)
7148#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7149#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7150#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7151#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7152#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7153#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7154#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7155#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7156#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7157#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7158
7159#define FSMC_BWTR1_BUSTURN_Pos (16U)
7160#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7161#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7162#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7163#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7164#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7165#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7166
7167#define FSMC_BWTR1_ACCMOD_Pos (28U)
7168#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7169#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7170#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7171#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7172
7173/****************** Bit definition for FSMC_BWTR2 register ******************/
7174#define FSMC_BWTR2_ADDSET_Pos (0U)
7175#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7176#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7177#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7178#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7179#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7180#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7181
7182#define FSMC_BWTR2_ADDHLD_Pos (4U)
7183#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7184#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7185#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7186#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7187#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7188#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7189
7190#define FSMC_BWTR2_DATAST_Pos (8U)
7191#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7192#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7193#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7194#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7195#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7196#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7197#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7198#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7199#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7200#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7201
7202#define FSMC_BWTR2_BUSTURN_Pos (16U)
7203#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7204#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7205#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7206#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7207#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7208#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7209
7210#define FSMC_BWTR2_ACCMOD_Pos (28U)
7211#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7212#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7213#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7214#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7215
7216/****************** Bit definition for FSMC_BWTR3 register ******************/
7217#define FSMC_BWTR3_ADDSET_Pos (0U)
7218#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7219#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7220#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7221#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7222#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7223#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7224
7225#define FSMC_BWTR3_ADDHLD_Pos (4U)
7226#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7227#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7228#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7229#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7230#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7231#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7232
7233#define FSMC_BWTR3_DATAST_Pos (8U)
7234#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7235#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7236#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7237#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7238#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7239#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7240#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7241#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7242#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7243#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7244
7245#define FSMC_BWTR3_BUSTURN_Pos (16U)
7246#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7247#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7248#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7249#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7250#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7251#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7252
7253#define FSMC_BWTR3_ACCMOD_Pos (28U)
7254#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7255#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7256#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7257#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7258
7259/****************** Bit definition for FSMC_BWTR4 register ******************/
7260#define FSMC_BWTR4_ADDSET_Pos (0U)
7261#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7262#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7263#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7264#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7265#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7266#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7267
7268#define FSMC_BWTR4_ADDHLD_Pos (4U)
7269#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7270#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7271#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7272#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7273#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7274#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7275
7276#define FSMC_BWTR4_DATAST_Pos (8U)
7277#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7278#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7279#define FSMC_BWTR4_DATAST_0 0x00000100U
7280#define FSMC_BWTR4_DATAST_1 0x00000200U
7281#define FSMC_BWTR4_DATAST_2 0x00000400U
7282#define FSMC_BWTR4_DATAST_3 0x00000800U
7283#define FSMC_BWTR4_DATAST_4 0x00001000U
7284#define FSMC_BWTR4_DATAST_5 0x00002000U
7285#define FSMC_BWTR4_DATAST_6 0x00004000U
7286#define FSMC_BWTR4_DATAST_7 0x00008000U
7287
7288#define FSMC_BWTR4_BUSTURN_Pos (16U)
7289#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7290#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7291#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7292#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7293#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7294#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7295
7296#define FSMC_BWTR4_ACCMOD_Pos (28U)
7297#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7298#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7299#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7300#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7301
7302/******************************************************************************/
7303/* */
7304/* General Purpose I/O */
7305/* */
7306/******************************************************************************/
7307/****************** Bits definition for GPIO_MODER register *****************/
7308#define GPIO_MODER_MODER0_Pos (0U)
7309#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
7310#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
7311#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
7312#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
7313#define GPIO_MODER_MODER1_Pos (2U)
7314#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
7315#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
7316#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
7317#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
7318#define GPIO_MODER_MODER2_Pos (4U)
7319#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
7320#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
7321#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
7322#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
7323#define GPIO_MODER_MODER3_Pos (6U)
7324#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
7325#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
7326#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
7327#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
7328#define GPIO_MODER_MODER4_Pos (8U)
7329#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
7330#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
7331#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
7332#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
7333#define GPIO_MODER_MODER5_Pos (10U)
7334#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
7335#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
7336#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
7337#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
7338#define GPIO_MODER_MODER6_Pos (12U)
7339#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
7340#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
7341#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
7342#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
7343#define GPIO_MODER_MODER7_Pos (14U)
7344#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
7345#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
7346#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
7347#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
7348#define GPIO_MODER_MODER8_Pos (16U)
7349#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
7350#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
7351#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
7352#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
7353#define GPIO_MODER_MODER9_Pos (18U)
7354#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
7355#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
7356#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
7357#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
7358#define GPIO_MODER_MODER10_Pos (20U)
7359#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
7360#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
7361#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
7362#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
7363#define GPIO_MODER_MODER11_Pos (22U)
7364#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
7365#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
7366#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
7367#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
7368#define GPIO_MODER_MODER12_Pos (24U)
7369#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
7370#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
7371#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
7372#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
7373#define GPIO_MODER_MODER13_Pos (26U)
7374#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
7375#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
7376#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
7377#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
7378#define GPIO_MODER_MODER14_Pos (28U)
7379#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
7380#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
7381#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
7382#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
7383#define GPIO_MODER_MODER15_Pos (30U)
7384#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
7385#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
7386#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
7387#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
7388
7389/* Legacy defines */
7390#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
7391#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
7392#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
7393#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
7394#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
7395#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
7396#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
7397#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
7398#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
7399#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
7400#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
7401#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
7402#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
7403#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
7404#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
7405#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
7406#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
7407#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
7408#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
7409#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
7410#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
7411#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
7412#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
7413#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
7414#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
7415#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
7416#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
7417#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
7418#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
7419#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
7420#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
7421#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
7422#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
7423#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
7424#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
7425#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
7426#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
7427#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
7428#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
7429#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
7430#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
7431#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
7432#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
7433#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
7434#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
7435#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
7436#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
7437#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
7438#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
7439#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
7440#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
7441#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
7442#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
7443#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
7444#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
7445#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
7446#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
7447#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
7448#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
7449#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
7450#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
7451#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
7452#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
7453#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
7454#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
7455#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
7456#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
7457#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
7458#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
7459#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
7460#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
7461#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
7462#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
7463#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
7464#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
7465#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
7466#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
7467#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
7468#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
7469#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
7470
7471/****************** Bits definition for GPIO_OTYPER register ****************/
7472#define GPIO_OTYPER_OT0_Pos (0U)
7473#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
7474#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7475#define GPIO_OTYPER_OT1_Pos (1U)
7476#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
7477#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7478#define GPIO_OTYPER_OT2_Pos (2U)
7479#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
7480#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7481#define GPIO_OTYPER_OT3_Pos (3U)
7482#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
7483#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7484#define GPIO_OTYPER_OT4_Pos (4U)
7485#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
7486#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7487#define GPIO_OTYPER_OT5_Pos (5U)
7488#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
7489#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7490#define GPIO_OTYPER_OT6_Pos (6U)
7491#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
7492#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7493#define GPIO_OTYPER_OT7_Pos (7U)
7494#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
7495#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7496#define GPIO_OTYPER_OT8_Pos (8U)
7497#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
7498#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7499#define GPIO_OTYPER_OT9_Pos (9U)
7500#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
7501#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7502#define GPIO_OTYPER_OT10_Pos (10U)
7503#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
7504#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7505#define GPIO_OTYPER_OT11_Pos (11U)
7506#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
7507#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7508#define GPIO_OTYPER_OT12_Pos (12U)
7509#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
7510#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7511#define GPIO_OTYPER_OT13_Pos (13U)
7512#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
7513#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7514#define GPIO_OTYPER_OT14_Pos (14U)
7515#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
7516#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7517#define GPIO_OTYPER_OT15_Pos (15U)
7518#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
7519#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7520
7521/* Legacy defines */
7522#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7523#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7524#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7525#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7526#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7527#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7528#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7529#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7530#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7531#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7532#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7533#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7534#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7535#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7536#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7537#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7538
7539/****************** Bits definition for GPIO_OSPEEDR register ***************/
7540#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7541#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
7542#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7543#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
7544#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
7545#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7546#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
7547#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7548#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
7549#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
7550#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7551#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
7552#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7553#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
7554#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
7555#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7556#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
7557#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7558#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
7559#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
7560#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7561#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
7562#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7563#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
7564#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
7565#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
7566#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
7567#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
7568#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
7569#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
7570#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
7571#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
7572#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
7573#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
7574#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
7575#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
7576#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
7577#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
7578#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
7579#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
7580#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
7581#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
7582#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
7583#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
7584#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
7585#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
7586#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
7587#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
7588#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
7589#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
7590#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
7591#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
7592#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
7593#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
7594#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
7595#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
7596#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
7597#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
7598#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
7599#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
7600#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
7601#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
7602#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
7603#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
7604#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
7605#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
7606#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
7607#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
7608#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
7609#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
7610#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
7611#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
7612#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
7613#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
7614#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
7615#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
7616#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
7617#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
7618#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
7619#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
7620
7621/* Legacy defines */
7622#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
7623#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
7624#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
7625#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
7626#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
7627#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
7628#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
7629#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
7630#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
7631#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
7632#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
7633#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
7634#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
7635#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
7636#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
7637#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
7638#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
7639#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
7640#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
7641#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
7642#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
7643#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
7644#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
7645#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
7646#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
7647#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
7648#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
7649#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
7650#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
7651#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
7652#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
7653#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
7654#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
7655#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
7656#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
7657#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
7658#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
7659#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
7660#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
7661#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
7662#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
7663#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
7664#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
7665#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
7666#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
7667#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
7668#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
7669#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
7670
7671/****************** Bits definition for GPIO_PUPDR register *****************/
7672#define GPIO_PUPDR_PUPD0_Pos (0U)
7673#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
7674#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
7675#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
7676#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
7677#define GPIO_PUPDR_PUPD1_Pos (2U)
7678#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
7679#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
7680#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
7681#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
7682#define GPIO_PUPDR_PUPD2_Pos (4U)
7683#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
7684#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
7685#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
7686#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
7687#define GPIO_PUPDR_PUPD3_Pos (6U)
7688#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
7689#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
7690#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
7691#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
7692#define GPIO_PUPDR_PUPD4_Pos (8U)
7693#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
7694#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
7695#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
7696#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
7697#define GPIO_PUPDR_PUPD5_Pos (10U)
7698#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
7699#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
7700#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
7701#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
7702#define GPIO_PUPDR_PUPD6_Pos (12U)
7703#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
7704#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
7705#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
7706#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
7707#define GPIO_PUPDR_PUPD7_Pos (14U)
7708#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
7709#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
7710#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
7711#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
7712#define GPIO_PUPDR_PUPD8_Pos (16U)
7713#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
7714#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
7715#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
7716#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
7717#define GPIO_PUPDR_PUPD9_Pos (18U)
7718#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
7719#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
7720#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
7721#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
7722#define GPIO_PUPDR_PUPD10_Pos (20U)
7723#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
7724#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
7725#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
7726#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
7727#define GPIO_PUPDR_PUPD11_Pos (22U)
7728#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
7729#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
7730#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
7731#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
7732#define GPIO_PUPDR_PUPD12_Pos (24U)
7733#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
7734#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
7735#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
7736#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
7737#define GPIO_PUPDR_PUPD13_Pos (26U)
7738#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
7739#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
7740#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
7741#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
7742#define GPIO_PUPDR_PUPD14_Pos (28U)
7743#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
7744#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
7745#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
7746#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
7747#define GPIO_PUPDR_PUPD15_Pos (30U)
7748#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
7749#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
7750#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
7751#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
7752
7753/* Legacy defines */
7754#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
7755#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
7756#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
7757#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
7758#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
7759#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
7760#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
7761#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
7762#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
7763#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
7764#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
7765#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
7766#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
7767#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
7768#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
7769#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
7770#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
7771#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
7772#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
7773#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
7774#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
7775#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
7776#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
7777#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
7778#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
7779#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
7780#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
7781#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
7782#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
7783#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
7784#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
7785#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
7786#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
7787#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
7788#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
7789#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
7790#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
7791#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
7792#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
7793#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
7794#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
7795#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
7796#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
7797#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
7798#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
7799#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
7800#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
7801#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
7802
7803/****************** Bits definition for GPIO_IDR register *******************/
7804#define GPIO_IDR_ID0_Pos (0U)
7805#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
7806#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
7807#define GPIO_IDR_ID1_Pos (1U)
7808#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
7809#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
7810#define GPIO_IDR_ID2_Pos (2U)
7811#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
7812#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
7813#define GPIO_IDR_ID3_Pos (3U)
7814#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
7815#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
7816#define GPIO_IDR_ID4_Pos (4U)
7817#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
7818#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
7819#define GPIO_IDR_ID5_Pos (5U)
7820#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
7821#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
7822#define GPIO_IDR_ID6_Pos (6U)
7823#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
7824#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
7825#define GPIO_IDR_ID7_Pos (7U)
7826#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
7827#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
7828#define GPIO_IDR_ID8_Pos (8U)
7829#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
7830#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
7831#define GPIO_IDR_ID9_Pos (9U)
7832#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
7833#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
7834#define GPIO_IDR_ID10_Pos (10U)
7835#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
7836#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
7837#define GPIO_IDR_ID11_Pos (11U)
7838#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
7839#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
7840#define GPIO_IDR_ID12_Pos (12U)
7841#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
7842#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
7843#define GPIO_IDR_ID13_Pos (13U)
7844#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
7845#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
7846#define GPIO_IDR_ID14_Pos (14U)
7847#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
7848#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
7849#define GPIO_IDR_ID15_Pos (15U)
7850#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
7851#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
7852
7853/* Legacy defines */
7854#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
7855#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
7856#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
7857#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
7858#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
7859#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
7860#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
7861#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
7862#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
7863#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
7864#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
7865#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
7866#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
7867#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
7868#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
7869#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
7870
7871/****************** Bits definition for GPIO_ODR register *******************/
7872#define GPIO_ODR_OD0_Pos (0U)
7873#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
7874#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
7875#define GPIO_ODR_OD1_Pos (1U)
7876#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
7877#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
7878#define GPIO_ODR_OD2_Pos (2U)
7879#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
7880#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
7881#define GPIO_ODR_OD3_Pos (3U)
7882#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
7883#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
7884#define GPIO_ODR_OD4_Pos (4U)
7885#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
7886#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
7887#define GPIO_ODR_OD5_Pos (5U)
7888#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
7889#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
7890#define GPIO_ODR_OD6_Pos (6U)
7891#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
7892#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
7893#define GPIO_ODR_OD7_Pos (7U)
7894#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
7895#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
7896#define GPIO_ODR_OD8_Pos (8U)
7897#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
7898#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
7899#define GPIO_ODR_OD9_Pos (9U)
7900#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
7901#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
7902#define GPIO_ODR_OD10_Pos (10U)
7903#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
7904#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
7905#define GPIO_ODR_OD11_Pos (11U)
7906#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
7907#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
7908#define GPIO_ODR_OD12_Pos (12U)
7909#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
7910#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
7911#define GPIO_ODR_OD13_Pos (13U)
7912#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
7913#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
7914#define GPIO_ODR_OD14_Pos (14U)
7915#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
7916#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
7917#define GPIO_ODR_OD15_Pos (15U)
7918#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
7919#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
7920/* Legacy defines */
7921#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
7922#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
7923#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
7924#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
7925#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
7926#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
7927#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
7928#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
7929#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
7930#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
7931#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
7932#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
7933#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
7934#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
7935#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
7936#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
7937
7938/****************** Bits definition for GPIO_BSRR register ******************/
7939#define GPIO_BSRR_BS0_Pos (0U)
7940#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
7941#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
7942#define GPIO_BSRR_BS1_Pos (1U)
7943#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
7944#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
7945#define GPIO_BSRR_BS2_Pos (2U)
7946#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
7947#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
7948#define GPIO_BSRR_BS3_Pos (3U)
7949#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
7950#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
7951#define GPIO_BSRR_BS4_Pos (4U)
7952#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
7953#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
7954#define GPIO_BSRR_BS5_Pos (5U)
7955#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
7956#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
7957#define GPIO_BSRR_BS6_Pos (6U)
7958#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
7959#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
7960#define GPIO_BSRR_BS7_Pos (7U)
7961#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
7962#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
7963#define GPIO_BSRR_BS8_Pos (8U)
7964#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
7965#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
7966#define GPIO_BSRR_BS9_Pos (9U)
7967#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
7968#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
7969#define GPIO_BSRR_BS10_Pos (10U)
7970#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
7971#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
7972#define GPIO_BSRR_BS11_Pos (11U)
7973#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
7974#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
7975#define GPIO_BSRR_BS12_Pos (12U)
7976#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
7977#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
7978#define GPIO_BSRR_BS13_Pos (13U)
7979#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
7980#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
7981#define GPIO_BSRR_BS14_Pos (14U)
7982#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
7983#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
7984#define GPIO_BSRR_BS15_Pos (15U)
7985#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
7986#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
7987#define GPIO_BSRR_BR0_Pos (16U)
7988#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
7989#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
7990#define GPIO_BSRR_BR1_Pos (17U)
7991#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
7992#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
7993#define GPIO_BSRR_BR2_Pos (18U)
7994#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
7995#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
7996#define GPIO_BSRR_BR3_Pos (19U)
7997#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
7998#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
7999#define GPIO_BSRR_BR4_Pos (20U)
8000#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8001#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8002#define GPIO_BSRR_BR5_Pos (21U)
8003#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8004#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8005#define GPIO_BSRR_BR6_Pos (22U)
8006#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8007#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8008#define GPIO_BSRR_BR7_Pos (23U)
8009#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8010#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8011#define GPIO_BSRR_BR8_Pos (24U)
8012#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8013#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8014#define GPIO_BSRR_BR9_Pos (25U)
8015#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8016#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8017#define GPIO_BSRR_BR10_Pos (26U)
8018#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8019#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8020#define GPIO_BSRR_BR11_Pos (27U)
8021#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8022#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8023#define GPIO_BSRR_BR12_Pos (28U)
8024#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8025#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8026#define GPIO_BSRR_BR13_Pos (29U)
8027#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8028#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8029#define GPIO_BSRR_BR14_Pos (30U)
8030#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8031#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8032#define GPIO_BSRR_BR15_Pos (31U)
8033#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8034#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8035
8036/* Legacy defines */
8037#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8038#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8039#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8040#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8041#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8042#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8043#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8044#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8045#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8046#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8047#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8048#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8049#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8050#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8051#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8052#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8053#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8054#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8055#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8056#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8057#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8058#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8059#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8060#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8061#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8062#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8063#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8064#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8065#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8066#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8067#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8068#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8069#define GPIO_BRR_BR0 GPIO_BSRR_BR0
8070#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8071#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8072#define GPIO_BRR_BR1 GPIO_BSRR_BR1
8073#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8074#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8075#define GPIO_BRR_BR2 GPIO_BSRR_BR2
8076#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8077#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8078#define GPIO_BRR_BR3 GPIO_BSRR_BR3
8079#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8080#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8081#define GPIO_BRR_BR4 GPIO_BSRR_BR4
8082#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8083#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8084#define GPIO_BRR_BR5 GPIO_BSRR_BR5
8085#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8086#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8087#define GPIO_BRR_BR6 GPIO_BSRR_BR6
8088#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8089#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8090#define GPIO_BRR_BR7 GPIO_BSRR_BR7
8091#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8092#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8093#define GPIO_BRR_BR8 GPIO_BSRR_BR8
8094#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8095#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8096#define GPIO_BRR_BR9 GPIO_BSRR_BR9
8097#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8098#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8099#define GPIO_BRR_BR10 GPIO_BSRR_BR10
8100#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8101#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8102#define GPIO_BRR_BR11 GPIO_BSRR_BR11
8103#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8104#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8105#define GPIO_BRR_BR12 GPIO_BSRR_BR12
8106#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8107#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8108#define GPIO_BRR_BR13 GPIO_BSRR_BR13
8109#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8110#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8111#define GPIO_BRR_BR14 GPIO_BSRR_BR14
8112#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8113#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8114#define GPIO_BRR_BR15 GPIO_BSRR_BR15
8115#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8116#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8117/****************** Bit definition for GPIO_LCKR register *********************/
8118#define GPIO_LCKR_LCK0_Pos (0U)
8119#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8120#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8121#define GPIO_LCKR_LCK1_Pos (1U)
8122#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8123#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8124#define GPIO_LCKR_LCK2_Pos (2U)
8125#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8126#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8127#define GPIO_LCKR_LCK3_Pos (3U)
8128#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8129#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8130#define GPIO_LCKR_LCK4_Pos (4U)
8131#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8132#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8133#define GPIO_LCKR_LCK5_Pos (5U)
8134#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8135#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8136#define GPIO_LCKR_LCK6_Pos (6U)
8137#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8138#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8139#define GPIO_LCKR_LCK7_Pos (7U)
8140#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8141#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8142#define GPIO_LCKR_LCK8_Pos (8U)
8143#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8144#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8145#define GPIO_LCKR_LCK9_Pos (9U)
8146#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8147#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8148#define GPIO_LCKR_LCK10_Pos (10U)
8149#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8150#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8151#define GPIO_LCKR_LCK11_Pos (11U)
8152#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8153#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8154#define GPIO_LCKR_LCK12_Pos (12U)
8155#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8156#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8157#define GPIO_LCKR_LCK13_Pos (13U)
8158#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8159#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8160#define GPIO_LCKR_LCK14_Pos (14U)
8161#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8162#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8163#define GPIO_LCKR_LCK15_Pos (15U)
8164#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8165#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8166#define GPIO_LCKR_LCKK_Pos (16U)
8167#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8168#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8169/****************** Bit definition for GPIO_AFRL register *********************/
8170#define GPIO_AFRL_AFSEL0_Pos (0U)
8171#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8172#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8173#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8174#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8175#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8176#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8177#define GPIO_AFRL_AFSEL1_Pos (4U)
8178#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8179#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8180#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8181#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8182#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8183#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8184#define GPIO_AFRL_AFSEL2_Pos (8U)
8185#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8186#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8187#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8188#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8189#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8190#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8191#define GPIO_AFRL_AFSEL3_Pos (12U)
8192#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8193#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8194#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8195#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8196#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8197#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8198#define GPIO_AFRL_AFSEL4_Pos (16U)
8199#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8200#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8201#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8202#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8203#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8204#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8205#define GPIO_AFRL_AFSEL5_Pos (20U)
8206#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8207#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8208#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8209#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8210#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8211#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8212#define GPIO_AFRL_AFSEL6_Pos (24U)
8213#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8214#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8215#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8216#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8217#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8218#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8219#define GPIO_AFRL_AFSEL7_Pos (28U)
8220#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8221#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8222#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8223#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8224#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8225#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8226
8227/* Legacy defines */
8228#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8229#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8230#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8231#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8232#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8233#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8234#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8235#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8236#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8237#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8238#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8239#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8240#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8241#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8242#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8243#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8244#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8245#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8246#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8247#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8248#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8249#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8250#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8251#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8252#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8253#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8254#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8255#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8256#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8257#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8258#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8259#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8260#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8261#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8262#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8263#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8264#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8265#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8266#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8267#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8268
8269/****************** Bit definition for GPIO_AFRH register *********************/
8270#define GPIO_AFRH_AFSEL8_Pos (0U)
8271#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
8272#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8273#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
8274#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
8275#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
8276#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
8277#define GPIO_AFRH_AFSEL9_Pos (4U)
8278#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
8279#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8280#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
8281#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
8282#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
8283#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
8284#define GPIO_AFRH_AFSEL10_Pos (8U)
8285#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
8286#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8287#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
8288#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
8289#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
8290#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
8291#define GPIO_AFRH_AFSEL11_Pos (12U)
8292#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
8293#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8294#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
8295#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
8296#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
8297#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
8298#define GPIO_AFRH_AFSEL12_Pos (16U)
8299#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
8300#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8301#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
8302#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
8303#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
8304#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
8305#define GPIO_AFRH_AFSEL13_Pos (20U)
8306#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
8307#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8308#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
8309#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
8310#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
8311#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
8312#define GPIO_AFRH_AFSEL14_Pos (24U)
8313#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
8314#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8315#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
8316#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
8317#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
8318#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
8319#define GPIO_AFRH_AFSEL15_Pos (28U)
8320#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
8321#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8322#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
8323#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
8324#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
8325#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
8326
8327/* Legacy defines */
8328#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8329#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8330#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8331#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8332#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8333#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8334#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8335#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8336#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8337#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8338#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8339#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8340#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8341#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8342#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8343#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8344#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8345#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8346#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8347#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8348#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8349#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8350#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8351#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8352#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8353#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8354#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8355#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8356#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8357#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8358#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8359#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8360#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8361#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8362#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8363#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8364#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8365#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8366#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8367#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8368
8369
8370/******************************************************************************/
8371/* */
8372/* Inter-integrated Circuit Interface */
8373/* */
8374/******************************************************************************/
8375/******************* Bit definition for I2C_CR1 register ********************/
8376#define I2C_CR1_PE_Pos (0U)
8377#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8378#define I2C_CR1_PE I2C_CR1_PE_Msk
8379#define I2C_CR1_SMBUS_Pos (1U)
8380#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
8381#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
8382#define I2C_CR1_SMBTYPE_Pos (3U)
8383#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
8384#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
8385#define I2C_CR1_ENARP_Pos (4U)
8386#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
8387#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
8388#define I2C_CR1_ENPEC_Pos (5U)
8389#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
8390#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
8391#define I2C_CR1_ENGC_Pos (6U)
8392#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
8393#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
8394#define I2C_CR1_NOSTRETCH_Pos (7U)
8395#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8396#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8397#define I2C_CR1_START_Pos (8U)
8398#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
8399#define I2C_CR1_START I2C_CR1_START_Msk
8400#define I2C_CR1_STOP_Pos (9U)
8401#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
8402#define I2C_CR1_STOP I2C_CR1_STOP_Msk
8403#define I2C_CR1_ACK_Pos (10U)
8404#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
8405#define I2C_CR1_ACK I2C_CR1_ACK_Msk
8406#define I2C_CR1_POS_Pos (11U)
8407#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
8408#define I2C_CR1_POS I2C_CR1_POS_Msk
8409#define I2C_CR1_PEC_Pos (12U)
8410#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
8411#define I2C_CR1_PEC I2C_CR1_PEC_Msk
8412#define I2C_CR1_ALERT_Pos (13U)
8413#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
8414#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
8415#define I2C_CR1_SWRST_Pos (15U)
8416#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
8417#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
8418
8419/******************* Bit definition for I2C_CR2 register ********************/
8420#define I2C_CR2_FREQ_Pos (0U)
8421#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
8422#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
8423#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
8424#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
8425#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
8426#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
8427#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
8428#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
8429
8430#define I2C_CR2_ITERREN_Pos (8U)
8431#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
8432#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
8433#define I2C_CR2_ITEVTEN_Pos (9U)
8434#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
8435#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
8436#define I2C_CR2_ITBUFEN_Pos (10U)
8437#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
8438#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
8439#define I2C_CR2_DMAEN_Pos (11U)
8440#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
8441#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
8442#define I2C_CR2_LAST_Pos (12U)
8443#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
8444#define I2C_CR2_LAST I2C_CR2_LAST_Msk
8445
8446/******************* Bit definition for I2C_OAR1 register *******************/
8447#define I2C_OAR1_ADD1_7 0x000000FEU
8448#define I2C_OAR1_ADD8_9 0x00000300U
8449
8450#define I2C_OAR1_ADD0_Pos (0U)
8451#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
8452#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
8453#define I2C_OAR1_ADD1_Pos (1U)
8454#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
8455#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
8456#define I2C_OAR1_ADD2_Pos (2U)
8457#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
8458#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
8459#define I2C_OAR1_ADD3_Pos (3U)
8460#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
8461#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
8462#define I2C_OAR1_ADD4_Pos (4U)
8463#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
8464#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
8465#define I2C_OAR1_ADD5_Pos (5U)
8466#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
8467#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
8468#define I2C_OAR1_ADD6_Pos (6U)
8469#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
8470#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
8471#define I2C_OAR1_ADD7_Pos (7U)
8472#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
8473#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
8474#define I2C_OAR1_ADD8_Pos (8U)
8475#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
8476#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
8477#define I2C_OAR1_ADD9_Pos (9U)
8478#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
8479#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
8480
8481#define I2C_OAR1_ADDMODE_Pos (15U)
8482#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
8483#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
8484
8485/******************* Bit definition for I2C_OAR2 register *******************/
8486#define I2C_OAR2_ENDUAL_Pos (0U)
8487#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
8488#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
8489#define I2C_OAR2_ADD2_Pos (1U)
8490#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
8491#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
8492
8493/******************** Bit definition for I2C_DR register ********************/
8494#define I2C_DR_DR_Pos (0U)
8495#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
8496#define I2C_DR_DR I2C_DR_DR_Msk
8497
8498/******************* Bit definition for I2C_SR1 register ********************/
8499#define I2C_SR1_SB_Pos (0U)
8500#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
8501#define I2C_SR1_SB I2C_SR1_SB_Msk
8502#define I2C_SR1_ADDR_Pos (1U)
8503#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
8504#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
8505#define I2C_SR1_BTF_Pos (2U)
8506#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
8507#define I2C_SR1_BTF I2C_SR1_BTF_Msk
8508#define I2C_SR1_ADD10_Pos (3U)
8509#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
8510#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
8511#define I2C_SR1_STOPF_Pos (4U)
8512#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
8513#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
8514#define I2C_SR1_RXNE_Pos (6U)
8515#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
8516#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
8517#define I2C_SR1_TXE_Pos (7U)
8518#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
8519#define I2C_SR1_TXE I2C_SR1_TXE_Msk
8520#define I2C_SR1_BERR_Pos (8U)
8521#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
8522#define I2C_SR1_BERR I2C_SR1_BERR_Msk
8523#define I2C_SR1_ARLO_Pos (9U)
8524#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
8525#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
8526#define I2C_SR1_AF_Pos (10U)
8527#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
8528#define I2C_SR1_AF I2C_SR1_AF_Msk
8529#define I2C_SR1_OVR_Pos (11U)
8530#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
8531#define I2C_SR1_OVR I2C_SR1_OVR_Msk
8532#define I2C_SR1_PECERR_Pos (12U)
8533#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
8534#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
8535#define I2C_SR1_TIMEOUT_Pos (14U)
8536#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
8537#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
8538#define I2C_SR1_SMBALERT_Pos (15U)
8539#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
8540#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
8541
8542/******************* Bit definition for I2C_SR2 register ********************/
8543#define I2C_SR2_MSL_Pos (0U)
8544#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
8545#define I2C_SR2_MSL I2C_SR2_MSL_Msk
8546#define I2C_SR2_BUSY_Pos (1U)
8547#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
8548#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
8549#define I2C_SR2_TRA_Pos (2U)
8550#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
8551#define I2C_SR2_TRA I2C_SR2_TRA_Msk
8552#define I2C_SR2_GENCALL_Pos (4U)
8553#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
8554#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
8555#define I2C_SR2_SMBDEFAULT_Pos (5U)
8556#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
8557#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
8558#define I2C_SR2_SMBHOST_Pos (6U)
8559#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
8560#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
8561#define I2C_SR2_DUALF_Pos (7U)
8562#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
8563#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
8564#define I2C_SR2_PEC_Pos (8U)
8565#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
8566#define I2C_SR2_PEC I2C_SR2_PEC_Msk
8567
8568/******************* Bit definition for I2C_CCR register ********************/
8569#define I2C_CCR_CCR_Pos (0U)
8570#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
8571#define I2C_CCR_CCR I2C_CCR_CCR_Msk
8572#define I2C_CCR_DUTY_Pos (14U)
8573#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
8574#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
8575#define I2C_CCR_FS_Pos (15U)
8576#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
8577#define I2C_CCR_FS I2C_CCR_FS_Msk
8578
8579/****************** Bit definition for I2C_TRISE register *******************/
8580#define I2C_TRISE_TRISE_Pos (0U)
8581#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
8582#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
8583
8584/****************** Bit definition for I2C_FLTR register *******************/
8585#define I2C_FLTR_DNF_Pos (0U)
8586#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
8587#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
8588#define I2C_FLTR_ANOFF_Pos (4U)
8589#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
8590#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
8591
8592/******************************************************************************/
8593/* */
8594/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
8595/* */
8596/******************************************************************************/
8597/******************* Bit definition for I2C_CR1 register *******************/
8598#define FMPI2C_CR1_PE_Pos (0U)
8599#define FMPI2C_CR1_PE_Msk (0x1UL << FMPI2C_CR1_PE_Pos)
8600#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk
8601#define FMPI2C_CR1_TXIE_Pos (1U)
8602#define FMPI2C_CR1_TXIE_Msk (0x1UL << FMPI2C_CR1_TXIE_Pos)
8603#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk
8604#define FMPI2C_CR1_RXIE_Pos (2U)
8605#define FMPI2C_CR1_RXIE_Msk (0x1UL << FMPI2C_CR1_RXIE_Pos)
8606#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk
8607#define FMPI2C_CR1_ADDRIE_Pos (3U)
8608#define FMPI2C_CR1_ADDRIE_Msk (0x1UL << FMPI2C_CR1_ADDRIE_Pos)
8609#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk
8610#define FMPI2C_CR1_NACKIE_Pos (4U)
8611#define FMPI2C_CR1_NACKIE_Msk (0x1UL << FMPI2C_CR1_NACKIE_Pos)
8612#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk
8613#define FMPI2C_CR1_STOPIE_Pos (5U)
8614#define FMPI2C_CR1_STOPIE_Msk (0x1UL << FMPI2C_CR1_STOPIE_Pos)
8615#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk
8616#define FMPI2C_CR1_TCIE_Pos (6U)
8617#define FMPI2C_CR1_TCIE_Msk (0x1UL << FMPI2C_CR1_TCIE_Pos)
8618#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk
8619#define FMPI2C_CR1_ERRIE_Pos (7U)
8620#define FMPI2C_CR1_ERRIE_Msk (0x1UL << FMPI2C_CR1_ERRIE_Pos)
8621#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk
8622#define FMPI2C_CR1_DNF_Pos (8U)
8623#define FMPI2C_CR1_DNF_Msk (0xFUL << FMPI2C_CR1_DNF_Pos)
8624#define FMPI2C_CR1_DNF FMPI2C_CR1_DNF_Msk
8625#define FMPI2C_CR1_ANFOFF_Pos (12U)
8626#define FMPI2C_CR1_ANFOFF_Msk (0x1UL << FMPI2C_CR1_ANFOFF_Pos)
8627#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk
8628#define FMPI2C_CR1_TXDMAEN_Pos (14U)
8629#define FMPI2C_CR1_TXDMAEN_Msk (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)
8630#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk
8631#define FMPI2C_CR1_RXDMAEN_Pos (15U)
8632#define FMPI2C_CR1_RXDMAEN_Msk (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)
8633#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk
8634#define FMPI2C_CR1_SBC_Pos (16U)
8635#define FMPI2C_CR1_SBC_Msk (0x1UL << FMPI2C_CR1_SBC_Pos)
8636#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk
8637#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
8638#define FMPI2C_CR1_NOSTRETCH_Msk (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)
8639#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk
8640#define FMPI2C_CR1_GCEN_Pos (19U)
8641#define FMPI2C_CR1_GCEN_Msk (0x1UL << FMPI2C_CR1_GCEN_Pos)
8642#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk
8643#define FMPI2C_CR1_SMBHEN_Pos (20U)
8644#define FMPI2C_CR1_SMBHEN_Msk (0x1UL << FMPI2C_CR1_SMBHEN_Pos)
8645#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk
8646#define FMPI2C_CR1_SMBDEN_Pos (21U)
8647#define FMPI2C_CR1_SMBDEN_Msk (0x1UL << FMPI2C_CR1_SMBDEN_Pos)
8648#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk
8649#define FMPI2C_CR1_ALERTEN_Pos (22U)
8650#define FMPI2C_CR1_ALERTEN_Msk (0x1UL << FMPI2C_CR1_ALERTEN_Pos)
8651#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk
8652#define FMPI2C_CR1_PECEN_Pos (23U)
8653#define FMPI2C_CR1_PECEN_Msk (0x1UL << FMPI2C_CR1_PECEN_Pos)
8654#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk
8655
8656/* Legacy Defines */
8657#define FMPI2C_CR1_DFN_Pos FMPI2C_CR1_DNF_Pos
8658#define FMPI2C_CR1_DFN_Msk FMPI2C_CR1_DNF_Msk
8659#define FMPI2C_CR1_DFN FMPI2C_CR1_DNF
8660/****************** Bit definition for I2C_CR2 register ********************/
8661#define FMPI2C_CR2_SADD_Pos (0U)
8662#define FMPI2C_CR2_SADD_Msk (0x3FFUL << FMPI2C_CR2_SADD_Pos)
8663#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk
8664#define FMPI2C_CR2_RD_WRN_Pos (10U)
8665#define FMPI2C_CR2_RD_WRN_Msk (0x1UL << FMPI2C_CR2_RD_WRN_Pos)
8666#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk
8667#define FMPI2C_CR2_ADD10_Pos (11U)
8668#define FMPI2C_CR2_ADD10_Msk (0x1UL << FMPI2C_CR2_ADD10_Pos)
8669#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk
8670#define FMPI2C_CR2_HEAD10R_Pos (12U)
8671#define FMPI2C_CR2_HEAD10R_Msk (0x1UL << FMPI2C_CR2_HEAD10R_Pos)
8672#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk
8673#define FMPI2C_CR2_START_Pos (13U)
8674#define FMPI2C_CR2_START_Msk (0x1UL << FMPI2C_CR2_START_Pos)
8675#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk
8676#define FMPI2C_CR2_STOP_Pos (14U)
8677#define FMPI2C_CR2_STOP_Msk (0x1UL << FMPI2C_CR2_STOP_Pos)
8678#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk
8679#define FMPI2C_CR2_NACK_Pos (15U)
8680#define FMPI2C_CR2_NACK_Msk (0x1UL << FMPI2C_CR2_NACK_Pos)
8681#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk
8682#define FMPI2C_CR2_NBYTES_Pos (16U)
8683#define FMPI2C_CR2_NBYTES_Msk (0xFFUL << FMPI2C_CR2_NBYTES_Pos)
8684#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk
8685#define FMPI2C_CR2_RELOAD_Pos (24U)
8686#define FMPI2C_CR2_RELOAD_Msk (0x1UL << FMPI2C_CR2_RELOAD_Pos)
8687#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk
8688#define FMPI2C_CR2_AUTOEND_Pos (25U)
8689#define FMPI2C_CR2_AUTOEND_Msk (0x1UL << FMPI2C_CR2_AUTOEND_Pos)
8690#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk
8691#define FMPI2C_CR2_PECBYTE_Pos (26U)
8692#define FMPI2C_CR2_PECBYTE_Msk (0x1UL << FMPI2C_CR2_PECBYTE_Pos)
8693#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk
8694
8695/******************* Bit definition for I2C_OAR1 register ******************/
8696#define FMPI2C_OAR1_OA1_Pos (0U)
8697#define FMPI2C_OAR1_OA1_Msk (0x3FFUL << FMPI2C_OAR1_OA1_Pos)
8698#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk
8699#define FMPI2C_OAR1_OA1MODE_Pos (10U)
8700#define FMPI2C_OAR1_OA1MODE_Msk (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)
8701#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk
8702#define FMPI2C_OAR1_OA1EN_Pos (15U)
8703#define FMPI2C_OAR1_OA1EN_Msk (0x1UL << FMPI2C_OAR1_OA1EN_Pos)
8704#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk
8705
8706/******************* Bit definition for I2C_OAR2 register ******************/
8707#define FMPI2C_OAR2_OA2_Pos (1U)
8708#define FMPI2C_OAR2_OA2_Msk (0x7FUL << FMPI2C_OAR2_OA2_Pos)
8709#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk
8710#define FMPI2C_OAR2_OA2MSK_Pos (8U)
8711#define FMPI2C_OAR2_OA2MSK_Msk (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)
8712#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk
8713#define FMPI2C_OAR2_OA2EN_Pos (15U)
8714#define FMPI2C_OAR2_OA2EN_Msk (0x1UL << FMPI2C_OAR2_OA2EN_Pos)
8715#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk
8716
8717/******************* Bit definition for I2C_TIMINGR register *******************/
8718#define FMPI2C_TIMINGR_SCLL_Pos (0U)
8719#define FMPI2C_TIMINGR_SCLL_Msk (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)
8720#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk
8721#define FMPI2C_TIMINGR_SCLH_Pos (8U)
8722#define FMPI2C_TIMINGR_SCLH_Msk (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)
8723#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk
8724#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
8725#define FMPI2C_TIMINGR_SDADEL_Msk (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)
8726#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk
8727#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
8728#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)
8729#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk
8730#define FMPI2C_TIMINGR_PRESC_Pos (28U)
8731#define FMPI2C_TIMINGR_PRESC_Msk (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)
8732#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk
8733
8734/******************* Bit definition for I2C_TIMEOUTR register *******************/
8735#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8736#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos)
8737#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk
8738#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
8739#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)
8740#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk
8741#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8742#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos)
8743#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk
8744#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8745#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)
8746#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk
8747#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
8748#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)
8749#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk
8750
8751/****************** Bit definition for I2C_ISR register *********************/
8752#define FMPI2C_ISR_TXE_Pos (0U)
8753#define FMPI2C_ISR_TXE_Msk (0x1UL << FMPI2C_ISR_TXE_Pos)
8754#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk
8755#define FMPI2C_ISR_TXIS_Pos (1U)
8756#define FMPI2C_ISR_TXIS_Msk (0x1UL << FMPI2C_ISR_TXIS_Pos)
8757#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk
8758#define FMPI2C_ISR_RXNE_Pos (2U)
8759#define FMPI2C_ISR_RXNE_Msk (0x1UL << FMPI2C_ISR_RXNE_Pos)
8760#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk
8761#define FMPI2C_ISR_ADDR_Pos (3U)
8762#define FMPI2C_ISR_ADDR_Msk (0x1UL << FMPI2C_ISR_ADDR_Pos)
8763#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk
8764#define FMPI2C_ISR_NACKF_Pos (4U)
8765#define FMPI2C_ISR_NACKF_Msk (0x1UL << FMPI2C_ISR_NACKF_Pos)
8766#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk
8767#define FMPI2C_ISR_STOPF_Pos (5U)
8768#define FMPI2C_ISR_STOPF_Msk (0x1UL << FMPI2C_ISR_STOPF_Pos)
8769#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk
8770#define FMPI2C_ISR_TC_Pos (6U)
8771#define FMPI2C_ISR_TC_Msk (0x1UL << FMPI2C_ISR_TC_Pos)
8772#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk
8773#define FMPI2C_ISR_TCR_Pos (7U)
8774#define FMPI2C_ISR_TCR_Msk (0x1UL << FMPI2C_ISR_TCR_Pos)
8775#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk
8776#define FMPI2C_ISR_BERR_Pos (8U)
8777#define FMPI2C_ISR_BERR_Msk (0x1UL << FMPI2C_ISR_BERR_Pos)
8778#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk
8779#define FMPI2C_ISR_ARLO_Pos (9U)
8780#define FMPI2C_ISR_ARLO_Msk (0x1UL << FMPI2C_ISR_ARLO_Pos)
8781#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk
8782#define FMPI2C_ISR_OVR_Pos (10U)
8783#define FMPI2C_ISR_OVR_Msk (0x1UL << FMPI2C_ISR_OVR_Pos)
8784#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk
8785#define FMPI2C_ISR_PECERR_Pos (11U)
8786#define FMPI2C_ISR_PECERR_Msk (0x1UL << FMPI2C_ISR_PECERR_Pos)
8787#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk
8788#define FMPI2C_ISR_TIMEOUT_Pos (12U)
8789#define FMPI2C_ISR_TIMEOUT_Msk (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)
8790#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk
8791#define FMPI2C_ISR_ALERT_Pos (13U)
8792#define FMPI2C_ISR_ALERT_Msk (0x1UL << FMPI2C_ISR_ALERT_Pos)
8793#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk
8794#define FMPI2C_ISR_BUSY_Pos (15U)
8795#define FMPI2C_ISR_BUSY_Msk (0x1UL << FMPI2C_ISR_BUSY_Pos)
8796#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk
8797#define FMPI2C_ISR_DIR_Pos (16U)
8798#define FMPI2C_ISR_DIR_Msk (0x1UL << FMPI2C_ISR_DIR_Pos)
8799#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk
8800#define FMPI2C_ISR_ADDCODE_Pos (17U)
8801#define FMPI2C_ISR_ADDCODE_Msk (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)
8802#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk
8803
8804/****************** Bit definition for I2C_ICR register *********************/
8805#define FMPI2C_ICR_ADDRCF_Pos (3U)
8806#define FMPI2C_ICR_ADDRCF_Msk (0x1UL << FMPI2C_ICR_ADDRCF_Pos)
8807#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk
8808#define FMPI2C_ICR_NACKCF_Pos (4U)
8809#define FMPI2C_ICR_NACKCF_Msk (0x1UL << FMPI2C_ICR_NACKCF_Pos)
8810#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk
8811#define FMPI2C_ICR_STOPCF_Pos (5U)
8812#define FMPI2C_ICR_STOPCF_Msk (0x1UL << FMPI2C_ICR_STOPCF_Pos)
8813#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk
8814#define FMPI2C_ICR_BERRCF_Pos (8U)
8815#define FMPI2C_ICR_BERRCF_Msk (0x1UL << FMPI2C_ICR_BERRCF_Pos)
8816#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk
8817#define FMPI2C_ICR_ARLOCF_Pos (9U)
8818#define FMPI2C_ICR_ARLOCF_Msk (0x1UL << FMPI2C_ICR_ARLOCF_Pos)
8819#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk
8820#define FMPI2C_ICR_OVRCF_Pos (10U)
8821#define FMPI2C_ICR_OVRCF_Msk (0x1UL << FMPI2C_ICR_OVRCF_Pos)
8822#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk
8823#define FMPI2C_ICR_PECCF_Pos (11U)
8824#define FMPI2C_ICR_PECCF_Msk (0x1UL << FMPI2C_ICR_PECCF_Pos)
8825#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk
8826#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
8827#define FMPI2C_ICR_TIMOUTCF_Msk (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)
8828#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk
8829#define FMPI2C_ICR_ALERTCF_Pos (13U)
8830#define FMPI2C_ICR_ALERTCF_Msk (0x1UL << FMPI2C_ICR_ALERTCF_Pos)
8831#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk
8832
8833/****************** Bit definition for I2C_PECR register *********************/
8834#define FMPI2C_PECR_PEC_Pos (0U)
8835#define FMPI2C_PECR_PEC_Msk (0xFFUL << FMPI2C_PECR_PEC_Pos)
8836#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk
8837
8838/****************** Bit definition for I2C_RXDR register *********************/
8839#define FMPI2C_RXDR_RXDATA_Pos (0U)
8840#define FMPI2C_RXDR_RXDATA_Msk (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)
8841#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk
8842
8843/****************** Bit definition for I2C_TXDR register *********************/
8844#define FMPI2C_TXDR_TXDATA_Pos (0U)
8845#define FMPI2C_TXDR_TXDATA_Msk (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)
8846#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk
8847
8848
8849
8850/******************************************************************************/
8851/* */
8852/* Independent WATCHDOG */
8853/* */
8854/******************************************************************************/
8855/******************* Bit definition for IWDG_KR register ********************/
8856#define IWDG_KR_KEY_Pos (0U)
8857#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
8858#define IWDG_KR_KEY IWDG_KR_KEY_Msk
8859
8860/******************* Bit definition for IWDG_PR register ********************/
8861#define IWDG_PR_PR_Pos (0U)
8862#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
8863#define IWDG_PR_PR IWDG_PR_PR_Msk
8864#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
8865#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
8866#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
8867
8868/******************* Bit definition for IWDG_RLR register *******************/
8869#define IWDG_RLR_RL_Pos (0U)
8870#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
8871#define IWDG_RLR_RL IWDG_RLR_RL_Msk
8872
8873/******************* Bit definition for IWDG_SR register ********************/
8874#define IWDG_SR_PVU_Pos (0U)
8875#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
8876#define IWDG_SR_PVU IWDG_SR_PVU_Msk
8877#define IWDG_SR_RVU_Pos (1U)
8878#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
8879#define IWDG_SR_RVU IWDG_SR_RVU_Msk
8880
8881
8882
8883/******************************************************************************/
8884/* */
8885/* Power Control */
8886/* */
8887/******************************************************************************/
8888/******************** Bit definition for PWR_CR register ********************/
8889#define PWR_CR_LPDS_Pos (0U)
8890#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
8891#define PWR_CR_LPDS PWR_CR_LPDS_Msk
8892#define PWR_CR_PDDS_Pos (1U)
8893#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
8894#define PWR_CR_PDDS PWR_CR_PDDS_Msk
8895#define PWR_CR_CWUF_Pos (2U)
8896#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
8897#define PWR_CR_CWUF PWR_CR_CWUF_Msk
8898#define PWR_CR_CSBF_Pos (3U)
8899#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
8900#define PWR_CR_CSBF PWR_CR_CSBF_Msk
8901#define PWR_CR_PVDE_Pos (4U)
8902#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
8903#define PWR_CR_PVDE PWR_CR_PVDE_Msk
8904
8905#define PWR_CR_PLS_Pos (5U)
8906#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
8907#define PWR_CR_PLS PWR_CR_PLS_Msk
8908#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
8909#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
8910#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
8911
8913#define PWR_CR_PLS_LEV0 0x00000000U
8914#define PWR_CR_PLS_LEV1 0x00000020U
8915#define PWR_CR_PLS_LEV2 0x00000040U
8916#define PWR_CR_PLS_LEV3 0x00000060U
8917#define PWR_CR_PLS_LEV4 0x00000080U
8918#define PWR_CR_PLS_LEV5 0x000000A0U
8919#define PWR_CR_PLS_LEV6 0x000000C0U
8920#define PWR_CR_PLS_LEV7 0x000000E0U
8921#define PWR_CR_DBP_Pos (8U)
8922#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
8923#define PWR_CR_DBP PWR_CR_DBP_Msk
8924#define PWR_CR_FPDS_Pos (9U)
8925#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
8926#define PWR_CR_FPDS PWR_CR_FPDS_Msk
8927#define PWR_CR_LPLVDS_Pos (10U)
8928#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
8929#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
8930#define PWR_CR_MRLVDS_Pos (11U)
8931#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
8932#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
8933#define PWR_CR_ADCDC1_Pos (13U)
8934#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
8935#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
8936#define PWR_CR_VOS_Pos (14U)
8937#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
8938#define PWR_CR_VOS PWR_CR_VOS_Msk
8939#define PWR_CR_VOS_0 0x00004000U
8940#define PWR_CR_VOS_1 0x00008000U
8941#define PWR_CR_FMSSR_Pos (20U)
8942#define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos)
8943#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk
8944#define PWR_CR_FISSR_Pos (21U)
8945#define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos)
8946#define PWR_CR_FISSR PWR_CR_FISSR_Msk
8947
8948
8949/******************* Bit definition for PWR_CSR register ********************/
8950#define PWR_CSR_WUF_Pos (0U)
8951#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
8952#define PWR_CSR_WUF PWR_CSR_WUF_Msk
8953#define PWR_CSR_SBF_Pos (1U)
8954#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
8955#define PWR_CSR_SBF PWR_CSR_SBF_Msk
8956#define PWR_CSR_PVDO_Pos (2U)
8957#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
8958#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
8959#define PWR_CSR_BRR_Pos (3U)
8960#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
8961#define PWR_CSR_BRR PWR_CSR_BRR_Msk
8962#define PWR_CSR_EWUP3_Pos (6U)
8963#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)
8964#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk
8965#define PWR_CSR_EWUP2_Pos (7U)
8966#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
8967#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
8968#define PWR_CSR_EWUP1_Pos (8U)
8969#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
8970#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
8971#define PWR_CSR_BRE_Pos (9U)
8972#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
8973#define PWR_CSR_BRE PWR_CSR_BRE_Msk
8974#define PWR_CSR_VOSRDY_Pos (14U)
8975#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
8976#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
8977
8978
8979/******************************************************************************/
8980/* */
8981/* QUADSPI */
8982/* */
8983/******************************************************************************/
8984/*
8985 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
8986 */
8987#define QSPI1_V2_1L
8988
8989/***************** Bit definition for QUADSPI_CR register *******************/
8990#define QUADSPI_CR_EN_Pos (0U)
8991#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
8992#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
8993#define QUADSPI_CR_ABORT_Pos (1U)
8994#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
8995#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
8996#define QUADSPI_CR_DMAEN_Pos (2U)
8997#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
8998#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
8999#define QUADSPI_CR_TCEN_Pos (3U)
9000#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
9001#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
9002#define QUADSPI_CR_SSHIFT_Pos (4U)
9003#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
9004#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
9005#define QUADSPI_CR_DFM_Pos (6U)
9006#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
9007#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
9008#define QUADSPI_CR_FSEL_Pos (7U)
9009#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
9010#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
9011#define QUADSPI_CR_FTHRES_Pos (8U)
9012#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
9013#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
9014#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
9015#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
9016#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
9017#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
9018#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
9019#define QUADSPI_CR_TEIE_Pos (16U)
9020#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
9021#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
9022#define QUADSPI_CR_TCIE_Pos (17U)
9023#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
9024#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
9025#define QUADSPI_CR_FTIE_Pos (18U)
9026#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
9027#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
9028#define QUADSPI_CR_SMIE_Pos (19U)
9029#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
9030#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
9031#define QUADSPI_CR_TOIE_Pos (20U)
9032#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
9033#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
9034#define QUADSPI_CR_APMS_Pos (22U)
9035#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
9036#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
9037#define QUADSPI_CR_PMM_Pos (23U)
9038#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
9039#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
9040#define QUADSPI_CR_PRESCALER_Pos (24U)
9041#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
9042#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
9043#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
9044#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
9045#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
9046#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
9047#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
9048#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
9049#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
9050#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
9051
9052/***************** Bit definition for QUADSPI_DCR register ******************/
9053#define QUADSPI_DCR_CKMODE_Pos (0U)
9054#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
9055#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
9056#define QUADSPI_DCR_CSHT_Pos (8U)
9057#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
9058#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
9059#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
9060#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
9061#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
9062#define QUADSPI_DCR_FSIZE_Pos (16U)
9063#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
9064#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
9065#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
9066#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
9067#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
9068#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
9069#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
9070
9071/****************** Bit definition for QUADSPI_SR register *******************/
9072#define QUADSPI_SR_TEF_Pos (0U)
9073#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
9074#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
9075#define QUADSPI_SR_TCF_Pos (1U)
9076#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
9077#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
9078#define QUADSPI_SR_FTF_Pos (2U)
9079#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
9080#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
9081#define QUADSPI_SR_SMF_Pos (3U)
9082#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
9083#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
9084#define QUADSPI_SR_TOF_Pos (4U)
9085#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
9086#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
9087#define QUADSPI_SR_BUSY_Pos (5U)
9088#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
9089#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
9090#define QUADSPI_SR_FLEVEL_Pos (8U)
9091#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
9092#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
9093#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
9094#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
9095#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
9096#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
9097#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
9098#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
9099
9100/****************** Bit definition for QUADSPI_FCR register ******************/
9101#define QUADSPI_FCR_CTEF_Pos (0U)
9102#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
9103#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
9104#define QUADSPI_FCR_CTCF_Pos (1U)
9105#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
9106#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
9107#define QUADSPI_FCR_CSMF_Pos (3U)
9108#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
9109#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
9110#define QUADSPI_FCR_CTOF_Pos (4U)
9111#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
9112#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
9113
9114/****************** Bit definition for QUADSPI_DLR register ******************/
9115#define QUADSPI_DLR_DL_Pos (0U)
9116#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
9117#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
9118
9119/****************** Bit definition for QUADSPI_CCR register ******************/
9120#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9121#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
9122#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
9123#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
9124#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
9125#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
9126#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
9127#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
9128#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
9129#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
9130#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
9131#define QUADSPI_CCR_IMODE_Pos (8U)
9132#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
9133#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
9134#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
9135#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
9136#define QUADSPI_CCR_ADMODE_Pos (10U)
9137#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
9138#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
9139#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
9140#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
9141#define QUADSPI_CCR_ADSIZE_Pos (12U)
9142#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
9143#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
9144#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
9145#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
9146#define QUADSPI_CCR_ABMODE_Pos (14U)
9147#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
9148#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
9149#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
9150#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
9151#define QUADSPI_CCR_ABSIZE_Pos (16U)
9152#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
9153#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
9154#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
9155#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
9156#define QUADSPI_CCR_DCYC_Pos (18U)
9157#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
9158#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
9159#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
9160#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
9161#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
9162#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
9163#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
9164#define QUADSPI_CCR_DMODE_Pos (24U)
9165#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
9166#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
9167#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
9168#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
9169#define QUADSPI_CCR_FMODE_Pos (26U)
9170#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
9171#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
9172#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
9173#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
9174#define QUADSPI_CCR_SIOO_Pos (28U)
9175#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
9176#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
9177#define QUADSPI_CCR_DHHC_Pos (30U)
9178#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
9179#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
9180#define QUADSPI_CCR_DDRM_Pos (31U)
9181#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
9182#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
9183/****************** Bit definition for QUADSPI_AR register *******************/
9184#define QUADSPI_AR_ADDRESS_Pos (0U)
9185#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
9186#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
9187
9188/****************** Bit definition for QUADSPI_ABR register ******************/
9189#define QUADSPI_ABR_ALTERNATE_Pos (0U)
9190#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
9191#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
9192
9193/****************** Bit definition for QUADSPI_DR register *******************/
9194#define QUADSPI_DR_DATA_Pos (0U)
9195#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
9196#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
9197
9198/****************** Bit definition for QUADSPI_PSMKR register ****************/
9199#define QUADSPI_PSMKR_MASK_Pos (0U)
9200#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
9201#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
9202
9203/****************** Bit definition for QUADSPI_PSMAR register ****************/
9204#define QUADSPI_PSMAR_MATCH_Pos (0U)
9205#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
9206#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
9207
9208/****************** Bit definition for QUADSPI_PIR register *****************/
9209#define QUADSPI_PIR_INTERVAL_Pos (0U)
9210#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
9211#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
9212
9213/****************** Bit definition for QUADSPI_LPTR register *****************/
9214#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
9215#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
9216#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
9217
9218/******************************************************************************/
9219/* */
9220/* Reset and Clock Control */
9221/* */
9222/******************************************************************************/
9223/******************** Bit definition for RCC_CR register ********************/
9224#define RCC_CR_HSION_Pos (0U)
9225#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9226#define RCC_CR_HSION RCC_CR_HSION_Msk
9227#define RCC_CR_HSIRDY_Pos (1U)
9228#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9229#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9230
9231#define RCC_CR_HSITRIM_Pos (3U)
9232#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9233#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9234#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9235#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9236#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9237#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9238#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9239
9240#define RCC_CR_HSICAL_Pos (8U)
9241#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9242#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9243#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9244#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9245#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9246#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9247#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9248#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9249#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9250#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9251
9252#define RCC_CR_HSEON_Pos (16U)
9253#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9254#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9255#define RCC_CR_HSERDY_Pos (17U)
9256#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9257#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9258#define RCC_CR_HSEBYP_Pos (18U)
9259#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9260#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9261#define RCC_CR_CSSON_Pos (19U)
9262#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9263#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9264#define RCC_CR_PLLON_Pos (24U)
9265#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9266#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9267#define RCC_CR_PLLRDY_Pos (25U)
9268#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9269#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9270/*
9271 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9272 */
9273#define RCC_PLLI2S_SUPPORT
9274
9275#define RCC_CR_PLLI2SON_Pos (26U)
9276#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9277#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9278#define RCC_CR_PLLI2SRDY_Pos (27U)
9279#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9280#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9281
9282/******************** Bit definition for RCC_PLLCFGR register ***************/
9283#define RCC_PLLCFGR_PLLM_Pos (0U)
9284#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9285#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9286#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9287#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9288#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9289#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9290#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9291#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9292
9293#define RCC_PLLCFGR_PLLN_Pos (6U)
9294#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9295#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9296#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9297#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9298#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9299#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9300#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9301#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9302#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9303#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9304#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9305
9306#define RCC_PLLCFGR_PLLP_Pos (16U)
9307#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9308#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9309#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9310#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9311
9312#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9313#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9314#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9315#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9316#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9317#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9318#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9319
9320#define RCC_PLLCFGR_PLLQ_Pos (24U)
9321#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9322#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9323#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9324#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9325#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9326#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9327/*
9328 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9329 */
9330#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT
9331
9332#define RCC_PLLCFGR_PLLR_Pos (28U)
9333#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
9334#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9335#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
9336#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
9337#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
9338
9339/******************** Bit definition for RCC_CFGR register ******************/
9341#define RCC_CFGR_SW_Pos (0U)
9342#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9343#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9344#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9345#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9346
9347#define RCC_CFGR_SW_HSI 0x00000000U
9348#define RCC_CFGR_SW_HSE 0x00000001U
9349#define RCC_CFGR_SW_PLL 0x00000002U
9350
9352#define RCC_CFGR_SWS_Pos (2U)
9353#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9354#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9355#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9356#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9357
9358#define RCC_CFGR_SWS_HSI 0x00000000U
9359#define RCC_CFGR_SWS_HSE 0x00000004U
9360#define RCC_CFGR_SWS_PLL 0x00000008U
9361
9363#define RCC_CFGR_HPRE_Pos (4U)
9364#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9365#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9366#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9367#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9368#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9369#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9370
9371#define RCC_CFGR_HPRE_DIV1 0x00000000U
9372#define RCC_CFGR_HPRE_DIV2 0x00000080U
9373#define RCC_CFGR_HPRE_DIV4 0x00000090U
9374#define RCC_CFGR_HPRE_DIV8 0x000000A0U
9375#define RCC_CFGR_HPRE_DIV16 0x000000B0U
9376#define RCC_CFGR_HPRE_DIV64 0x000000C0U
9377#define RCC_CFGR_HPRE_DIV128 0x000000D0U
9378#define RCC_CFGR_HPRE_DIV256 0x000000E0U
9379#define RCC_CFGR_HPRE_DIV512 0x000000F0U
9380
9382#define RCC_CFGR_PPRE1_Pos (10U)
9383#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9384#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9385#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9386#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9387#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9388
9389#define RCC_CFGR_PPRE1_DIV1 0x00000000U
9390#define RCC_CFGR_PPRE1_DIV2 0x00001000U
9391#define RCC_CFGR_PPRE1_DIV4 0x00001400U
9392#define RCC_CFGR_PPRE1_DIV8 0x00001800U
9393#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9394
9396#define RCC_CFGR_PPRE2_Pos (13U)
9397#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9398#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9399#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9400#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9401#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9402
9403#define RCC_CFGR_PPRE2_DIV1 0x00000000U
9404#define RCC_CFGR_PPRE2_DIV2 0x00008000U
9405#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9406#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9407#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9408
9410#define RCC_CFGR_RTCPRE_Pos (16U)
9411#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9412#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9413#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9414#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9415#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9416#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9417#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9418
9420#define RCC_CFGR_MCO1_Pos (21U)
9421#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9422#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9423#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9424#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9425
9426
9427#define RCC_CFGR_MCO1PRE_Pos (24U)
9428#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9429#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9430#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9431#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9432#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9433
9434#define RCC_CFGR_MCO2PRE_Pos (27U)
9435#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9436#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9437#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9438#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9439#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9440
9441#define RCC_CFGR_MCO2_Pos (30U)
9442#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9443#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9444#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9445#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9446
9447/******************** Bit definition for RCC_CIR register *******************/
9448#define RCC_CIR_LSIRDYF_Pos (0U)
9449#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9450#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9451#define RCC_CIR_LSERDYF_Pos (1U)
9452#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9453#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9454#define RCC_CIR_HSIRDYF_Pos (2U)
9455#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9456#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9457#define RCC_CIR_HSERDYF_Pos (3U)
9458#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9459#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9460#define RCC_CIR_PLLRDYF_Pos (4U)
9461#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9462#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9463#define RCC_CIR_PLLI2SRDYF_Pos (5U)
9464#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9465#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9466
9467#define RCC_CIR_CSSF_Pos (7U)
9468#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9469#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9470#define RCC_CIR_LSIRDYIE_Pos (8U)
9471#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9472#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9473#define RCC_CIR_LSERDYIE_Pos (9U)
9474#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9475#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9476#define RCC_CIR_HSIRDYIE_Pos (10U)
9477#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9478#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9479#define RCC_CIR_HSERDYIE_Pos (11U)
9480#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9481#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9482#define RCC_CIR_PLLRDYIE_Pos (12U)
9483#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9484#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9485#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9486#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9487#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9488
9489#define RCC_CIR_LSIRDYC_Pos (16U)
9490#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9491#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9492#define RCC_CIR_LSERDYC_Pos (17U)
9493#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9494#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9495#define RCC_CIR_HSIRDYC_Pos (18U)
9496#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9497#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9498#define RCC_CIR_HSERDYC_Pos (19U)
9499#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9500#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9501#define RCC_CIR_PLLRDYC_Pos (20U)
9502#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9503#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9504#define RCC_CIR_PLLI2SRDYC_Pos (21U)
9505#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9506#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9507
9508#define RCC_CIR_CSSC_Pos (23U)
9509#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9510#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9511
9512/******************** Bit definition for RCC_AHB1RSTR register **************/
9513#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9514#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9515#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9516#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9517#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9518#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9519#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9520#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9521#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9522#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9523#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9524#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9525#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9526#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9527#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9528#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9529#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9530#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9531#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9532#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9533#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9534#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9535#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9536#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9537#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9538#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9539#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9540
9541/******************** Bit definition for RCC_AHB2RSTR register **************/
9542#define RCC_AHB2RSTR_RNGRST_Pos (6U)
9543#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9544#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9545#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9546#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9547#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9548/******************** Bit definition for RCC_AHB3RSTR register **************/
9549#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9550#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9551#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9552#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
9553#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
9554#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9555
9556
9557/******************** Bit definition for RCC_APB1RSTR register **************/
9558#define RCC_APB1RSTR_TIM2RST_Pos (0U)
9559#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9560#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9561#define RCC_APB1RSTR_TIM3RST_Pos (1U)
9562#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9563#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9564#define RCC_APB1RSTR_TIM4RST_Pos (2U)
9565#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9566#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9567#define RCC_APB1RSTR_TIM5RST_Pos (3U)
9568#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9569#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9570#define RCC_APB1RSTR_TIM6RST_Pos (4U)
9571#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9572#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9573#define RCC_APB1RSTR_TIM7RST_Pos (5U)
9574#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9575#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9576#define RCC_APB1RSTR_TIM12RST_Pos (6U)
9577#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9578#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9579#define RCC_APB1RSTR_TIM13RST_Pos (7U)
9580#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9581#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9582#define RCC_APB1RSTR_TIM14RST_Pos (8U)
9583#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9584#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9585#define RCC_APB1RSTR_WWDGRST_Pos (11U)
9586#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9587#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9588#define RCC_APB1RSTR_SPI2RST_Pos (14U)
9589#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9590#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9591#define RCC_APB1RSTR_SPI3RST_Pos (15U)
9592#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9593#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9594#define RCC_APB1RSTR_USART2RST_Pos (17U)
9595#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9596#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9597#define RCC_APB1RSTR_USART3RST_Pos (18U)
9598#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9599#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9600#define RCC_APB1RSTR_I2C1RST_Pos (21U)
9601#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9602#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9603#define RCC_APB1RSTR_I2C2RST_Pos (22U)
9604#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9605#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9606#define RCC_APB1RSTR_I2C3RST_Pos (23U)
9607#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9608#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9609#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
9610#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos)
9611#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
9612#define RCC_APB1RSTR_CAN1RST_Pos (25U)
9613#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9614#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9615#define RCC_APB1RSTR_CAN2RST_Pos (26U)
9616#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9617#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9618#define RCC_APB1RSTR_PWRRST_Pos (28U)
9619#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9620#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9621
9622/******************** Bit definition for RCC_APB2RSTR register **************/
9623#define RCC_APB2RSTR_TIM1RST_Pos (0U)
9624#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9625#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9626#define RCC_APB2RSTR_TIM8RST_Pos (1U)
9627#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9628#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9629#define RCC_APB2RSTR_USART1RST_Pos (4U)
9630#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9631#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9632#define RCC_APB2RSTR_USART6RST_Pos (5U)
9633#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9634#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9635#define RCC_APB2RSTR_ADCRST_Pos (8U)
9636#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9637#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9638#define RCC_APB2RSTR_SDIORST_Pos (11U)
9639#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9640#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9641#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9642#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9643#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9644#define RCC_APB2RSTR_SPI4RST_Pos (13U)
9645#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
9646#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
9647#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9648#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9649#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9650#define RCC_APB2RSTR_TIM9RST_Pos (16U)
9651#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9652#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9653#define RCC_APB2RSTR_TIM10RST_Pos (17U)
9654#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9655#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9656#define RCC_APB2RSTR_TIM11RST_Pos (18U)
9657#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9658#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9659#define RCC_APB2RSTR_SPI5RST_Pos (20U)
9660#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
9661#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
9662#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
9663#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
9664#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
9665
9666/******************** Bit definition for RCC_AHB1ENR register ***************/
9667#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9668#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9669#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9670#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9671#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9672#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9673#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9674#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9675#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9676#define RCC_AHB1ENR_GPIODEN_Pos (3U)
9677#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9678#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9679#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9680#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9681#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9682#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9683#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9684#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9685#define RCC_AHB1ENR_CRCEN_Pos (12U)
9686#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9687#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9688#define RCC_AHB1ENR_DMA1EN_Pos (21U)
9689#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9690#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9691#define RCC_AHB1ENR_DMA2EN_Pos (22U)
9692#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9693#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9694/******************** Bit definition for RCC_AHB2ENR register ***************/
9695/*
9696 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9697 */
9698#define RCC_AHB2_SUPPORT
9699
9700#define RCC_AHB2ENR_RNGEN_Pos (6U)
9701#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9702#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9703#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9704#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9705#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9706
9707/******************** Bit definition for RCC_AHB3ENR register ***************/
9708/*
9709 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9710 */
9711#define RCC_AHB3_SUPPORT
9712
9713#define RCC_AHB3ENR_FSMCEN_Pos (0U)
9714#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
9715#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9716#define RCC_AHB3ENR_QSPIEN_Pos (1U)
9717#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
9718#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
9719
9720/******************** Bit definition for RCC_APB1ENR register ***************/
9721#define RCC_APB1ENR_TIM2EN_Pos (0U)
9722#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
9723#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9724#define RCC_APB1ENR_TIM3EN_Pos (1U)
9725#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
9726#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9727#define RCC_APB1ENR_TIM4EN_Pos (2U)
9728#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
9729#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9730#define RCC_APB1ENR_TIM5EN_Pos (3U)
9731#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
9732#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9733#define RCC_APB1ENR_TIM6EN_Pos (4U)
9734#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
9735#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9736#define RCC_APB1ENR_TIM7EN_Pos (5U)
9737#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
9738#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9739#define RCC_APB1ENR_TIM12EN_Pos (6U)
9740#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
9741#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9742#define RCC_APB1ENR_TIM13EN_Pos (7U)
9743#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
9744#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9745#define RCC_APB1ENR_TIM14EN_Pos (8U)
9746#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
9747#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9748#define RCC_APB1ENR_RTCAPBEN_Pos (10U)
9749#define RCC_APB1ENR_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)
9750#define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
9751#define RCC_APB1ENR_WWDGEN_Pos (11U)
9752#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
9753#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9754#define RCC_APB1ENR_SPI2EN_Pos (14U)
9755#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
9756#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9757#define RCC_APB1ENR_SPI3EN_Pos (15U)
9758#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
9759#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
9760#define RCC_APB1ENR_USART2EN_Pos (17U)
9761#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
9762#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
9763#define RCC_APB1ENR_USART3EN_Pos (18U)
9764#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
9765#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
9766#define RCC_APB1ENR_I2C1EN_Pos (21U)
9767#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
9768#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
9769#define RCC_APB1ENR_I2C2EN_Pos (22U)
9770#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
9771#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
9772#define RCC_APB1ENR_I2C3EN_Pos (23U)
9773#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
9774#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
9775#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
9776#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos)
9777#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
9778#define RCC_APB1ENR_CAN1EN_Pos (25U)
9779#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
9780#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
9781#define RCC_APB1ENR_CAN2EN_Pos (26U)
9782#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
9783#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
9784#define RCC_APB1ENR_PWREN_Pos (28U)
9785#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
9786#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
9787
9788/******************** Bit definition for RCC_APB2ENR register ***************/
9789#define RCC_APB2ENR_TIM1EN_Pos (0U)
9790#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
9791#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9792#define RCC_APB2ENR_TIM8EN_Pos (1U)
9793#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
9794#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
9795#define RCC_APB2ENR_USART1EN_Pos (4U)
9796#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
9797#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9798#define RCC_APB2ENR_USART6EN_Pos (5U)
9799#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
9800#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
9801#define RCC_APB2ENR_ADC1EN_Pos (8U)
9802#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
9803#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
9804#define RCC_APB2ENR_SDIOEN_Pos (11U)
9805#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
9806#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
9807#define RCC_APB2ENR_SPI1EN_Pos (12U)
9808#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
9809#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9810#define RCC_APB2ENR_SPI4EN_Pos (13U)
9811#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
9812#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
9813#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
9814#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
9815#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9816#define RCC_APB2ENR_EXTITEN_Pos (15U)
9817#define RCC_APB2ENR_EXTITEN_Msk (0x1UL << RCC_APB2ENR_EXTITEN_Pos)
9818#define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
9819#define RCC_APB2ENR_TIM9EN_Pos (16U)
9820#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
9821#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
9822#define RCC_APB2ENR_TIM10EN_Pos (17U)
9823#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
9824#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
9825#define RCC_APB2ENR_TIM11EN_Pos (18U)
9826#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
9827#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
9828#define RCC_APB2ENR_SPI5EN_Pos (20U)
9829#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
9830#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
9831#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
9832#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
9833#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
9834
9835/******************** Bit definition for RCC_AHB1LPENR register *************/
9836#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
9837#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
9838#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
9839#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
9840#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
9841#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
9842#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
9843#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
9844#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
9845#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
9846#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
9847#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
9848#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
9849#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
9850#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
9851#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
9852#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
9853#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
9854#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
9855#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
9856#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
9857#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
9858#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
9859#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
9860#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
9861#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
9862#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
9863#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
9864#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
9865#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
9866#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
9867#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
9868#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
9869
9870
9871/******************** Bit definition for RCC_AHB2LPENR register *************/
9872#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
9873#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
9874#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
9875#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
9876#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
9877#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
9878
9879/******************** Bit definition for RCC_AHB3LPENR register *************/
9880#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
9881#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
9882#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
9883#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
9884#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
9885#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
9886
9887/******************** Bit definition for RCC_APB1LPENR register *************/
9888#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
9889#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
9890#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
9891#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
9892#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
9893#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
9894#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
9895#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
9896#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
9897#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
9898#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
9899#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
9900#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
9901#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
9902#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
9903#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
9904#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
9905#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
9906#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
9907#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
9908#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
9909#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
9910#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
9911#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
9912#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
9913#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
9914#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
9915#define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
9916#define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos)
9917#define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
9918#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
9919#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
9920#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
9921#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
9922#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
9923#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
9924#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
9925#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
9926#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
9927#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
9928#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
9929#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
9930#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
9931#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
9932#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
9933#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
9934#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
9935#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
9936#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
9937#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
9938#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
9939#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
9940#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
9941#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
9942#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
9943#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos)
9944#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
9945#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
9946#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
9947#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
9948#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
9949#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
9950#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
9951#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
9952#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
9953#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
9954
9955/******************** Bit definition for RCC_APB2LPENR register *************/
9956#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
9957#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
9958#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
9959#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
9960#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
9961#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
9962#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
9963#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
9964#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
9965#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
9966#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
9967#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
9968#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
9969#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
9970#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
9971#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
9972#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
9973#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
9974#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
9975#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
9976#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
9977#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
9978#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
9979#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
9980#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
9981#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
9982#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
9983#define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
9984#define RCC_APB2LPENR_EXTITLPEN_Msk (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos)
9985#define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
9986#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
9987#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
9988#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
9989#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
9990#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
9991#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
9992#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
9993#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
9994#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
9995#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
9996#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
9997#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
9998#define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
9999#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
10000#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
10001
10002/******************** Bit definition for RCC_BDCR register ******************/
10003#define RCC_BDCR_LSEON_Pos (0U)
10004#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10005#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10006#define RCC_BDCR_LSERDY_Pos (1U)
10007#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10008#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10009#define RCC_BDCR_LSEBYP_Pos (2U)
10010#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10011#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10012#define RCC_BDCR_LSEMOD_Pos (3U)
10013#define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
10014#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
10015
10016#define RCC_BDCR_RTCSEL_Pos (8U)
10017#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10018#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10019#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10020#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10021
10022#define RCC_BDCR_RTCEN_Pos (15U)
10023#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10024#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10025#define RCC_BDCR_BDRST_Pos (16U)
10026#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10027#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10028
10029/******************** Bit definition for RCC_CSR register *******************/
10030#define RCC_CSR_LSION_Pos (0U)
10031#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10032#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10033#define RCC_CSR_LSIRDY_Pos (1U)
10034#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10035#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10036#define RCC_CSR_RMVF_Pos (24U)
10037#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10038#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10039#define RCC_CSR_BORRSTF_Pos (25U)
10040#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10041#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10042#define RCC_CSR_PINRSTF_Pos (26U)
10043#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10044#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10045#define RCC_CSR_PORRSTF_Pos (27U)
10046#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10047#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10048#define RCC_CSR_SFTRSTF_Pos (28U)
10049#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10050#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10051#define RCC_CSR_IWDGRSTF_Pos (29U)
10052#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10053#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10054#define RCC_CSR_WWDGRSTF_Pos (30U)
10055#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10056#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10057#define RCC_CSR_LPWRRSTF_Pos (31U)
10058#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10059#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10060/* Legacy defines */
10061#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10062#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10063
10064/******************** Bit definition for RCC_SSCGR register *****************/
10065#define RCC_SSCGR_MODPER_Pos (0U)
10066#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10067#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10068#define RCC_SSCGR_INCSTEP_Pos (13U)
10069#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10070#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10071#define RCC_SSCGR_SPREADSEL_Pos (30U)
10072#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10073#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10074#define RCC_SSCGR_SSCGEN_Pos (31U)
10075#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10076#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10077
10078/******************** Bit definition for RCC_PLLI2SCFGR register ************/
10079#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
10080#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10081#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
10082#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10083#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10084#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10085#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10086#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10087#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10088
10089#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10090#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10091#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10092#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10093#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10094#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10095#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10096#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10097#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10098#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10099#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10100#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10101
10102#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
10103#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos)
10104#define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
10105#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
10106#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10107#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
10108#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10109#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10110#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10111#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10112#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10113#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10114#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10115#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10116#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10117#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10118
10119/******************** Bit definition for RCC_DCKCFGR register ***************/
10120
10121#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
10122#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos)
10123#define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
10124#define RCC_DCKCFGR_TIMPRE_Pos (24U)
10125#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
10126#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
10127#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
10128#define RCC_DCKCFGR_I2S1SRC_Msk (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)
10129#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
10130#define RCC_DCKCFGR_I2S1SRC_0 (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)
10131#define RCC_DCKCFGR_I2S1SRC_1 (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)
10132
10133#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
10134#define RCC_DCKCFGR_I2S2SRC_Msk (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)
10135#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
10136#define RCC_DCKCFGR_I2S2SRC_0 (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)
10137#define RCC_DCKCFGR_I2S2SRC_1 (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)
10138#define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
10139#define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos)
10140#define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
10141
10142/******************** Bit definition for RCC_CKGATENR register ***************/
10143#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
10144#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos)
10145#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
10146#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
10147#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos)
10148#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
10149#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
10150#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos)
10151#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
10152#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
10153#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos)
10154#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
10155#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
10156#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos)
10157#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
10158#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
10159#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos)
10160#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
10161#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
10162#define RCC_CKGATENR_RCC_CKEN_Msk (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos)
10163#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
10164#define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
10165#define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos)
10166#define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
10167
10168/******************** Bit definition for RCC_DCKCFGR2 register ***************/
10169#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
10170#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10171#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
10172#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10173#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10174#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
10175#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
10176#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
10177#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
10178#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)
10179#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
10180
10181
10182/******************************************************************************/
10183/* */
10184/* RNG */
10185/* */
10186/******************************************************************************/
10187/******************** Bits definition for RNG_CR register *******************/
10188#define RNG_CR_RNGEN_Pos (2U)
10189#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10190#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10191#define RNG_CR_IE_Pos (3U)
10192#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10193#define RNG_CR_IE RNG_CR_IE_Msk
10194
10195/******************** Bits definition for RNG_SR register *******************/
10196#define RNG_SR_DRDY_Pos (0U)
10197#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10198#define RNG_SR_DRDY RNG_SR_DRDY_Msk
10199#define RNG_SR_CECS_Pos (1U)
10200#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10201#define RNG_SR_CECS RNG_SR_CECS_Msk
10202#define RNG_SR_SECS_Pos (2U)
10203#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10204#define RNG_SR_SECS RNG_SR_SECS_Msk
10205#define RNG_SR_CEIS_Pos (5U)
10206#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10207#define RNG_SR_CEIS RNG_SR_CEIS_Msk
10208#define RNG_SR_SEIS_Pos (6U)
10209#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10210#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10211
10212/******************************************************************************/
10213/* */
10214/* Real-Time Clock (RTC) */
10215/* */
10216/******************************************************************************/
10217/******************** Bits definition for RTC_TR register *******************/
10218#define RTC_TR_PM_Pos (22U)
10219#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10220#define RTC_TR_PM RTC_TR_PM_Msk
10221#define RTC_TR_HT_Pos (20U)
10222#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10223#define RTC_TR_HT RTC_TR_HT_Msk
10224#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10225#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10226#define RTC_TR_HU_Pos (16U)
10227#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10228#define RTC_TR_HU RTC_TR_HU_Msk
10229#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10230#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10231#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10232#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10233#define RTC_TR_MNT_Pos (12U)
10234#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10235#define RTC_TR_MNT RTC_TR_MNT_Msk
10236#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10237#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10238#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10239#define RTC_TR_MNU_Pos (8U)
10240#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10241#define RTC_TR_MNU RTC_TR_MNU_Msk
10242#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10243#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10244#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10245#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10246#define RTC_TR_ST_Pos (4U)
10247#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10248#define RTC_TR_ST RTC_TR_ST_Msk
10249#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10250#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10251#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10252#define RTC_TR_SU_Pos (0U)
10253#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10254#define RTC_TR_SU RTC_TR_SU_Msk
10255#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10256#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10257#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10258#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10259
10260/******************** Bits definition for RTC_DR register *******************/
10261#define RTC_DR_YT_Pos (20U)
10262#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10263#define RTC_DR_YT RTC_DR_YT_Msk
10264#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10265#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10266#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10267#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10268#define RTC_DR_YU_Pos (16U)
10269#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10270#define RTC_DR_YU RTC_DR_YU_Msk
10271#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10272#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10273#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10274#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10275#define RTC_DR_WDU_Pos (13U)
10276#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10277#define RTC_DR_WDU RTC_DR_WDU_Msk
10278#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10279#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10280#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10281#define RTC_DR_MT_Pos (12U)
10282#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10283#define RTC_DR_MT RTC_DR_MT_Msk
10284#define RTC_DR_MU_Pos (8U)
10285#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10286#define RTC_DR_MU RTC_DR_MU_Msk
10287#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10288#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10289#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10290#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10291#define RTC_DR_DT_Pos (4U)
10292#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10293#define RTC_DR_DT RTC_DR_DT_Msk
10294#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10295#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10296#define RTC_DR_DU_Pos (0U)
10297#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10298#define RTC_DR_DU RTC_DR_DU_Msk
10299#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10300#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10301#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10302#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10303
10304/******************** Bits definition for RTC_CR register *******************/
10305#define RTC_CR_COE_Pos (23U)
10306#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10307#define RTC_CR_COE RTC_CR_COE_Msk
10308#define RTC_CR_OSEL_Pos (21U)
10309#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10310#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10311#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10312#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10313#define RTC_CR_POL_Pos (20U)
10314#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10315#define RTC_CR_POL RTC_CR_POL_Msk
10316#define RTC_CR_COSEL_Pos (19U)
10317#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10318#define RTC_CR_COSEL RTC_CR_COSEL_Msk
10319#define RTC_CR_BKP_Pos (18U)
10320#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10321#define RTC_CR_BKP RTC_CR_BKP_Msk
10322#define RTC_CR_SUB1H_Pos (17U)
10323#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10324#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10325#define RTC_CR_ADD1H_Pos (16U)
10326#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10327#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10328#define RTC_CR_TSIE_Pos (15U)
10329#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10330#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10331#define RTC_CR_WUTIE_Pos (14U)
10332#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10333#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10334#define RTC_CR_ALRBIE_Pos (13U)
10335#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10336#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10337#define RTC_CR_ALRAIE_Pos (12U)
10338#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10339#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10340#define RTC_CR_TSE_Pos (11U)
10341#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10342#define RTC_CR_TSE RTC_CR_TSE_Msk
10343#define RTC_CR_WUTE_Pos (10U)
10344#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10345#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10346#define RTC_CR_ALRBE_Pos (9U)
10347#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10348#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10349#define RTC_CR_ALRAE_Pos (8U)
10350#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10351#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10352#define RTC_CR_DCE_Pos (7U)
10353#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10354#define RTC_CR_DCE RTC_CR_DCE_Msk
10355#define RTC_CR_FMT_Pos (6U)
10356#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10357#define RTC_CR_FMT RTC_CR_FMT_Msk
10358#define RTC_CR_BYPSHAD_Pos (5U)
10359#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10360#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10361#define RTC_CR_REFCKON_Pos (4U)
10362#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10363#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10364#define RTC_CR_TSEDGE_Pos (3U)
10365#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10366#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10367#define RTC_CR_WUCKSEL_Pos (0U)
10368#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10369#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10370#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10371#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10372#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10373
10374/* Legacy defines */
10375#define RTC_CR_BCK RTC_CR_BKP
10376
10377/******************** Bits definition for RTC_ISR register ******************/
10378#define RTC_ISR_RECALPF_Pos (16U)
10379#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10380#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10381#define RTC_ISR_TAMP1F_Pos (13U)
10382#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10383#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10384#define RTC_ISR_TAMP2F_Pos (14U)
10385#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10386#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10387#define RTC_ISR_TSOVF_Pos (12U)
10388#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10389#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10390#define RTC_ISR_TSF_Pos (11U)
10391#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10392#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10393#define RTC_ISR_WUTF_Pos (10U)
10394#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10395#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10396#define RTC_ISR_ALRBF_Pos (9U)
10397#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10398#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10399#define RTC_ISR_ALRAF_Pos (8U)
10400#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10401#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10402#define RTC_ISR_INIT_Pos (7U)
10403#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10404#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10405#define RTC_ISR_INITF_Pos (6U)
10406#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10407#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10408#define RTC_ISR_RSF_Pos (5U)
10409#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10410#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10411#define RTC_ISR_INITS_Pos (4U)
10412#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10413#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10414#define RTC_ISR_SHPF_Pos (3U)
10415#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10416#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10417#define RTC_ISR_WUTWF_Pos (2U)
10418#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10419#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10420#define RTC_ISR_ALRBWF_Pos (1U)
10421#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10422#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10423#define RTC_ISR_ALRAWF_Pos (0U)
10424#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10425#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10426
10427/******************** Bits definition for RTC_PRER register *****************/
10428#define RTC_PRER_PREDIV_A_Pos (16U)
10429#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10430#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10431#define RTC_PRER_PREDIV_S_Pos (0U)
10432#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10433#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10434
10435/******************** Bits definition for RTC_WUTR register *****************/
10436#define RTC_WUTR_WUT_Pos (0U)
10437#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10438#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10439
10440/******************** Bits definition for RTC_CALIBR register ***************/
10441#define RTC_CALIBR_DCS_Pos (7U)
10442#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10443#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10444#define RTC_CALIBR_DC_Pos (0U)
10445#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10446#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10447
10448/******************** Bits definition for RTC_ALRMAR register ***************/
10449#define RTC_ALRMAR_MSK4_Pos (31U)
10450#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10451#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10452#define RTC_ALRMAR_WDSEL_Pos (30U)
10453#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10454#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10455#define RTC_ALRMAR_DT_Pos (28U)
10456#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10457#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10458#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10459#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10460#define RTC_ALRMAR_DU_Pos (24U)
10461#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10462#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10463#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10464#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10465#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10466#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10467#define RTC_ALRMAR_MSK3_Pos (23U)
10468#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10469#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10470#define RTC_ALRMAR_PM_Pos (22U)
10471#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10472#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10473#define RTC_ALRMAR_HT_Pos (20U)
10474#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10475#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10476#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10477#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10478#define RTC_ALRMAR_HU_Pos (16U)
10479#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10480#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10481#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10482#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10483#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10484#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10485#define RTC_ALRMAR_MSK2_Pos (15U)
10486#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10487#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10488#define RTC_ALRMAR_MNT_Pos (12U)
10489#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10490#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10491#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10492#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10493#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10494#define RTC_ALRMAR_MNU_Pos (8U)
10495#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10496#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10497#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10498#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10499#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10500#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10501#define RTC_ALRMAR_MSK1_Pos (7U)
10502#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10503#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10504#define RTC_ALRMAR_ST_Pos (4U)
10505#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10506#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10507#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10508#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10509#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10510#define RTC_ALRMAR_SU_Pos (0U)
10511#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10512#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10513#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10514#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10515#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10516#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10517
10518/******************** Bits definition for RTC_ALRMBR register ***************/
10519#define RTC_ALRMBR_MSK4_Pos (31U)
10520#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10521#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10522#define RTC_ALRMBR_WDSEL_Pos (30U)
10523#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10524#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10525#define RTC_ALRMBR_DT_Pos (28U)
10526#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10527#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10528#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10529#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10530#define RTC_ALRMBR_DU_Pos (24U)
10531#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10532#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10533#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10534#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10535#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10536#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10537#define RTC_ALRMBR_MSK3_Pos (23U)
10538#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10539#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10540#define RTC_ALRMBR_PM_Pos (22U)
10541#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10542#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10543#define RTC_ALRMBR_HT_Pos (20U)
10544#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10545#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10546#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10547#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10548#define RTC_ALRMBR_HU_Pos (16U)
10549#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10550#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10551#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10552#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10553#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10554#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10555#define RTC_ALRMBR_MSK2_Pos (15U)
10556#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10557#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10558#define RTC_ALRMBR_MNT_Pos (12U)
10559#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10560#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10561#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10562#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10563#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10564#define RTC_ALRMBR_MNU_Pos (8U)
10565#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10566#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10567#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10568#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10569#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10570#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10571#define RTC_ALRMBR_MSK1_Pos (7U)
10572#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10573#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10574#define RTC_ALRMBR_ST_Pos (4U)
10575#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10576#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10577#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10578#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10579#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10580#define RTC_ALRMBR_SU_Pos (0U)
10581#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10582#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10583#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10584#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10585#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10586#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10587
10588/******************** Bits definition for RTC_WPR register ******************/
10589#define RTC_WPR_KEY_Pos (0U)
10590#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10591#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10592
10593/******************** Bits definition for RTC_SSR register ******************/
10594#define RTC_SSR_SS_Pos (0U)
10595#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10596#define RTC_SSR_SS RTC_SSR_SS_Msk
10597
10598/******************** Bits definition for RTC_SHIFTR register ***************/
10599#define RTC_SHIFTR_SUBFS_Pos (0U)
10600#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
10601#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10602#define RTC_SHIFTR_ADD1S_Pos (31U)
10603#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
10604#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10605
10606/******************** Bits definition for RTC_TSTR register *****************/
10607#define RTC_TSTR_PM_Pos (22U)
10608#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10609#define RTC_TSTR_PM RTC_TSTR_PM_Msk
10610#define RTC_TSTR_HT_Pos (20U)
10611#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10612#define RTC_TSTR_HT RTC_TSTR_HT_Msk
10613#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10614#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10615#define RTC_TSTR_HU_Pos (16U)
10616#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10617#define RTC_TSTR_HU RTC_TSTR_HU_Msk
10618#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10619#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10620#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10621#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10622#define RTC_TSTR_MNT_Pos (12U)
10623#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10624#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10625#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10626#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10627#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10628#define RTC_TSTR_MNU_Pos (8U)
10629#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10630#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10631#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10632#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10633#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10634#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10635#define RTC_TSTR_ST_Pos (4U)
10636#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10637#define RTC_TSTR_ST RTC_TSTR_ST_Msk
10638#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10639#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10640#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10641#define RTC_TSTR_SU_Pos (0U)
10642#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10643#define RTC_TSTR_SU RTC_TSTR_SU_Msk
10644#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10645#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10646#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10647#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10648
10649/******************** Bits definition for RTC_TSDR register *****************/
10650#define RTC_TSDR_WDU_Pos (13U)
10651#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10652#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10653#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10654#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10655#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10656#define RTC_TSDR_MT_Pos (12U)
10657#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10658#define RTC_TSDR_MT RTC_TSDR_MT_Msk
10659#define RTC_TSDR_MU_Pos (8U)
10660#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10661#define RTC_TSDR_MU RTC_TSDR_MU_Msk
10662#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10663#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10664#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10665#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10666#define RTC_TSDR_DT_Pos (4U)
10667#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10668#define RTC_TSDR_DT RTC_TSDR_DT_Msk
10669#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10670#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10671#define RTC_TSDR_DU_Pos (0U)
10672#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10673#define RTC_TSDR_DU RTC_TSDR_DU_Msk
10674#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10675#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10676#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10677#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10678
10679/******************** Bits definition for RTC_TSSSR register ****************/
10680#define RTC_TSSSR_SS_Pos (0U)
10681#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
10682#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10683
10684/******************** Bits definition for RTC_CAL register *****************/
10685#define RTC_CALR_CALP_Pos (15U)
10686#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
10687#define RTC_CALR_CALP RTC_CALR_CALP_Msk
10688#define RTC_CALR_CALW8_Pos (14U)
10689#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
10690#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10691#define RTC_CALR_CALW16_Pos (13U)
10692#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
10693#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10694#define RTC_CALR_CALM_Pos (0U)
10695#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
10696#define RTC_CALR_CALM RTC_CALR_CALM_Msk
10697#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
10698#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
10699#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
10700#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
10701#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
10702#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
10703#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
10704#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
10705#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
10706
10707/******************** Bits definition for RTC_TAFCR register ****************/
10708#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10709#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
10710#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10711#define RTC_TAFCR_TSINSEL_Pos (17U)
10712#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
10713#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10714#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10715#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
10716#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10717#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10718#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
10719#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10720#define RTC_TAFCR_TAMPPRCH_Pos (13U)
10721#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
10722#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10723#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
10724#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
10725#define RTC_TAFCR_TAMPFLT_Pos (11U)
10726#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
10727#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10728#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
10729#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
10730#define RTC_TAFCR_TAMPFREQ_Pos (8U)
10731#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
10732#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10733#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
10734#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
10735#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
10736#define RTC_TAFCR_TAMPTS_Pos (7U)
10737#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
10738#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10739#define RTC_TAFCR_TAMP2TRG_Pos (4U)
10740#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
10741#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10742#define RTC_TAFCR_TAMP2E_Pos (3U)
10743#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
10744#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10745#define RTC_TAFCR_TAMPIE_Pos (2U)
10746#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
10747#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10748#define RTC_TAFCR_TAMP1TRG_Pos (1U)
10749#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
10750#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10751#define RTC_TAFCR_TAMP1E_Pos (0U)
10752#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
10753#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10754
10755/* Legacy defines */
10756#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10757
10758/******************** Bits definition for RTC_ALRMASSR register *************/
10759#define RTC_ALRMASSR_MASKSS_Pos (24U)
10760#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
10761#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10762#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
10763#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
10764#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
10765#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
10766#define RTC_ALRMASSR_SS_Pos (0U)
10767#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
10768#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10769
10770/******************** Bits definition for RTC_ALRMBSSR register *************/
10771#define RTC_ALRMBSSR_MASKSS_Pos (24U)
10772#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
10773#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10774#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
10775#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
10776#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
10777#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
10778#define RTC_ALRMBSSR_SS_Pos (0U)
10779#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
10780#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10781
10782/******************** Bits definition for RTC_BKP0R register ****************/
10783#define RTC_BKP0R_Pos (0U)
10784#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10785#define RTC_BKP0R RTC_BKP0R_Msk
10786
10787/******************** Bits definition for RTC_BKP1R register ****************/
10788#define RTC_BKP1R_Pos (0U)
10789#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10790#define RTC_BKP1R RTC_BKP1R_Msk
10791
10792/******************** Bits definition for RTC_BKP2R register ****************/
10793#define RTC_BKP2R_Pos (0U)
10794#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10795#define RTC_BKP2R RTC_BKP2R_Msk
10796
10797/******************** Bits definition for RTC_BKP3R register ****************/
10798#define RTC_BKP3R_Pos (0U)
10799#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
10800#define RTC_BKP3R RTC_BKP3R_Msk
10801
10802/******************** Bits definition for RTC_BKP4R register ****************/
10803#define RTC_BKP4R_Pos (0U)
10804#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
10805#define RTC_BKP4R RTC_BKP4R_Msk
10806
10807/******************** Bits definition for RTC_BKP5R register ****************/
10808#define RTC_BKP5R_Pos (0U)
10809#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
10810#define RTC_BKP5R RTC_BKP5R_Msk
10811
10812/******************** Bits definition for RTC_BKP6R register ****************/
10813#define RTC_BKP6R_Pos (0U)
10814#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
10815#define RTC_BKP6R RTC_BKP6R_Msk
10816
10817/******************** Bits definition for RTC_BKP7R register ****************/
10818#define RTC_BKP7R_Pos (0U)
10819#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
10820#define RTC_BKP7R RTC_BKP7R_Msk
10821
10822/******************** Bits definition for RTC_BKP8R register ****************/
10823#define RTC_BKP8R_Pos (0U)
10824#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
10825#define RTC_BKP8R RTC_BKP8R_Msk
10826
10827/******************** Bits definition for RTC_BKP9R register ****************/
10828#define RTC_BKP9R_Pos (0U)
10829#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
10830#define RTC_BKP9R RTC_BKP9R_Msk
10831
10832/******************** Bits definition for RTC_BKP10R register ***************/
10833#define RTC_BKP10R_Pos (0U)
10834#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
10835#define RTC_BKP10R RTC_BKP10R_Msk
10836
10837/******************** Bits definition for RTC_BKP11R register ***************/
10838#define RTC_BKP11R_Pos (0U)
10839#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
10840#define RTC_BKP11R RTC_BKP11R_Msk
10841
10842/******************** Bits definition for RTC_BKP12R register ***************/
10843#define RTC_BKP12R_Pos (0U)
10844#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
10845#define RTC_BKP12R RTC_BKP12R_Msk
10846
10847/******************** Bits definition for RTC_BKP13R register ***************/
10848#define RTC_BKP13R_Pos (0U)
10849#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
10850#define RTC_BKP13R RTC_BKP13R_Msk
10851
10852/******************** Bits definition for RTC_BKP14R register ***************/
10853#define RTC_BKP14R_Pos (0U)
10854#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
10855#define RTC_BKP14R RTC_BKP14R_Msk
10856
10857/******************** Bits definition for RTC_BKP15R register ***************/
10858#define RTC_BKP15R_Pos (0U)
10859#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
10860#define RTC_BKP15R RTC_BKP15R_Msk
10861
10862/******************** Bits definition for RTC_BKP16R register ***************/
10863#define RTC_BKP16R_Pos (0U)
10864#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
10865#define RTC_BKP16R RTC_BKP16R_Msk
10866
10867/******************** Bits definition for RTC_BKP17R register ***************/
10868#define RTC_BKP17R_Pos (0U)
10869#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
10870#define RTC_BKP17R RTC_BKP17R_Msk
10871
10872/******************** Bits definition for RTC_BKP18R register ***************/
10873#define RTC_BKP18R_Pos (0U)
10874#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
10875#define RTC_BKP18R RTC_BKP18R_Msk
10876
10877/******************** Bits definition for RTC_BKP19R register ***************/
10878#define RTC_BKP19R_Pos (0U)
10879#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
10880#define RTC_BKP19R RTC_BKP19R_Msk
10881
10882/******************** Number of backup registers ******************************/
10883#define RTC_BKP_NUMBER 0x000000014U
10884
10885
10886/******************************************************************************/
10887/* */
10888/* SD host Interface */
10889/* */
10890/******************************************************************************/
10891/****************** Bit definition for SDIO_POWER register ******************/
10892#define SDIO_POWER_PWRCTRL_Pos (0U)
10893#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
10894#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
10895#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
10896#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
10897
10898/****************** Bit definition for SDIO_CLKCR register ******************/
10899#define SDIO_CLKCR_CLKDIV_Pos (0U)
10900#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
10901#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
10902#define SDIO_CLKCR_CLKEN_Pos (8U)
10903#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
10904#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
10905#define SDIO_CLKCR_PWRSAV_Pos (9U)
10906#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
10907#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
10908#define SDIO_CLKCR_BYPASS_Pos (10U)
10909#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
10910#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
10911
10912#define SDIO_CLKCR_WIDBUS_Pos (11U)
10913#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
10914#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
10915#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
10916#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
10917
10918#define SDIO_CLKCR_NEGEDGE_Pos (13U)
10919#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
10920#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
10921#define SDIO_CLKCR_HWFC_EN_Pos (14U)
10922#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
10923#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
10924
10925/******************* Bit definition for SDIO_ARG register *******************/
10926#define SDIO_ARG_CMDARG_Pos (0U)
10927#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
10928#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
10929
10930/******************* Bit definition for SDIO_CMD register *******************/
10931#define SDIO_CMD_CMDINDEX_Pos (0U)
10932#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
10933#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
10934
10935#define SDIO_CMD_WAITRESP_Pos (6U)
10936#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
10937#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
10938#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
10939#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
10940
10941#define SDIO_CMD_WAITINT_Pos (8U)
10942#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
10943#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
10944#define SDIO_CMD_WAITPEND_Pos (9U)
10945#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
10946#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
10947#define SDIO_CMD_CPSMEN_Pos (10U)
10948#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
10949#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
10950#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
10951#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
10952#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
10953
10954/***************** Bit definition for SDIO_RESPCMD register *****************/
10955#define SDIO_RESPCMD_RESPCMD_Pos (0U)
10956#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
10957#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
10958
10959/****************** Bit definition for SDIO_RESP0 register ******************/
10960#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
10961#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
10962#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
10963
10964/****************** Bit definition for SDIO_RESP1 register ******************/
10965#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
10966#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
10967#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
10968
10969/****************** Bit definition for SDIO_RESP2 register ******************/
10970#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
10971#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
10972#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
10973
10974/****************** Bit definition for SDIO_RESP3 register ******************/
10975#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
10976#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
10977#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
10978
10979/****************** Bit definition for SDIO_RESP4 register ******************/
10980#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
10981#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
10982#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
10983
10984/****************** Bit definition for SDIO_DTIMER register *****************/
10985#define SDIO_DTIMER_DATATIME_Pos (0U)
10986#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
10987#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
10988
10989/****************** Bit definition for SDIO_DLEN register *******************/
10990#define SDIO_DLEN_DATALENGTH_Pos (0U)
10991#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
10992#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
10993
10994/****************** Bit definition for SDIO_DCTRL register ******************/
10995#define SDIO_DCTRL_DTEN_Pos (0U)
10996#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
10997#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
10998#define SDIO_DCTRL_DTDIR_Pos (1U)
10999#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
11000#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
11001#define SDIO_DCTRL_DTMODE_Pos (2U)
11002#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
11003#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
11004#define SDIO_DCTRL_DMAEN_Pos (3U)
11005#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
11006#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
11007
11008#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11009#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11010#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
11011#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11012#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11013#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11014#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11015
11016#define SDIO_DCTRL_RWSTART_Pos (8U)
11017#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
11018#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
11019#define SDIO_DCTRL_RWSTOP_Pos (9U)
11020#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
11021#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
11022#define SDIO_DCTRL_RWMOD_Pos (10U)
11023#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
11024#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
11025#define SDIO_DCTRL_SDIOEN_Pos (11U)
11026#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
11027#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
11028
11029/****************** Bit definition for SDIO_DCOUNT register *****************/
11030#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11031#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
11032#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
11033
11034/****************** Bit definition for SDIO_STA register ********************/
11035#define SDIO_STA_CCRCFAIL_Pos (0U)
11036#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
11037#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
11038#define SDIO_STA_DCRCFAIL_Pos (1U)
11039#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
11040#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
11041#define SDIO_STA_CTIMEOUT_Pos (2U)
11042#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
11043#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
11044#define SDIO_STA_DTIMEOUT_Pos (3U)
11045#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
11046#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
11047#define SDIO_STA_TXUNDERR_Pos (4U)
11048#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
11049#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
11050#define SDIO_STA_RXOVERR_Pos (5U)
11051#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
11052#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
11053#define SDIO_STA_CMDREND_Pos (6U)
11054#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
11055#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
11056#define SDIO_STA_CMDSENT_Pos (7U)
11057#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
11058#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
11059#define SDIO_STA_DATAEND_Pos (8U)
11060#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
11061#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
11062#define SDIO_STA_DBCKEND_Pos (10U)
11063#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
11064#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
11065#define SDIO_STA_CMDACT_Pos (11U)
11066#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
11067#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
11068#define SDIO_STA_TXACT_Pos (12U)
11069#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
11070#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
11071#define SDIO_STA_RXACT_Pos (13U)
11072#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
11073#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
11074#define SDIO_STA_TXFIFOHE_Pos (14U)
11075#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
11076#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
11077#define SDIO_STA_RXFIFOHF_Pos (15U)
11078#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
11079#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
11080#define SDIO_STA_TXFIFOF_Pos (16U)
11081#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
11082#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
11083#define SDIO_STA_RXFIFOF_Pos (17U)
11084#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
11085#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
11086#define SDIO_STA_TXFIFOE_Pos (18U)
11087#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
11088#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
11089#define SDIO_STA_RXFIFOE_Pos (19U)
11090#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
11091#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
11092#define SDIO_STA_TXDAVL_Pos (20U)
11093#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
11094#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
11095#define SDIO_STA_RXDAVL_Pos (21U)
11096#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
11097#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
11098#define SDIO_STA_SDIOIT_Pos (22U)
11099#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
11100#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
11101
11102/******************* Bit definition for SDIO_ICR register *******************/
11103#define SDIO_ICR_CCRCFAILC_Pos (0U)
11104#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
11105#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
11106#define SDIO_ICR_DCRCFAILC_Pos (1U)
11107#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
11108#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
11109#define SDIO_ICR_CTIMEOUTC_Pos (2U)
11110#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
11111#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
11112#define SDIO_ICR_DTIMEOUTC_Pos (3U)
11113#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
11114#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
11115#define SDIO_ICR_TXUNDERRC_Pos (4U)
11116#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
11117#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
11118#define SDIO_ICR_RXOVERRC_Pos (5U)
11119#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
11120#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
11121#define SDIO_ICR_CMDRENDC_Pos (6U)
11122#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
11123#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
11124#define SDIO_ICR_CMDSENTC_Pos (7U)
11125#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
11126#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
11127#define SDIO_ICR_DATAENDC_Pos (8U)
11128#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
11129#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
11130#define SDIO_ICR_DBCKENDC_Pos (10U)
11131#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
11132#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
11133#define SDIO_ICR_SDIOITC_Pos (22U)
11134#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
11135#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
11136
11137/****************** Bit definition for SDIO_MASK register *******************/
11138#define SDIO_MASK_CCRCFAILIE_Pos (0U)
11139#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
11140#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
11141#define SDIO_MASK_DCRCFAILIE_Pos (1U)
11142#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
11143#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
11144#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11145#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
11146#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
11147#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11148#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
11149#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
11150#define SDIO_MASK_TXUNDERRIE_Pos (4U)
11151#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
11152#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
11153#define SDIO_MASK_RXOVERRIE_Pos (5U)
11154#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
11155#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
11156#define SDIO_MASK_CMDRENDIE_Pos (6U)
11157#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
11158#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
11159#define SDIO_MASK_CMDSENTIE_Pos (7U)
11160#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
11161#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
11162#define SDIO_MASK_DATAENDIE_Pos (8U)
11163#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
11164#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
11165#define SDIO_MASK_DBCKENDIE_Pos (10U)
11166#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
11167#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
11168#define SDIO_MASK_CMDACTIE_Pos (11U)
11169#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
11170#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
11171#define SDIO_MASK_TXACTIE_Pos (12U)
11172#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
11173#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
11174#define SDIO_MASK_RXACTIE_Pos (13U)
11175#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
11176#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
11177#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11178#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
11179#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
11180#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11181#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
11182#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
11183#define SDIO_MASK_TXFIFOFIE_Pos (16U)
11184#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
11185#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
11186#define SDIO_MASK_RXFIFOFIE_Pos (17U)
11187#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
11188#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
11189#define SDIO_MASK_TXFIFOEIE_Pos (18U)
11190#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
11191#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
11192#define SDIO_MASK_RXFIFOEIE_Pos (19U)
11193#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
11194#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
11195#define SDIO_MASK_TXDAVLIE_Pos (20U)
11196#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
11197#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
11198#define SDIO_MASK_RXDAVLIE_Pos (21U)
11199#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
11200#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
11201#define SDIO_MASK_SDIOITIE_Pos (22U)
11202#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
11203#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
11204
11205/***************** Bit definition for SDIO_FIFOCNT register *****************/
11206#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11207#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
11208#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
11209
11210/****************** Bit definition for SDIO_FIFO register *******************/
11211#define SDIO_FIFO_FIFODATA_Pos (0U)
11212#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
11213#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
11214
11215/******************************************************************************/
11216/* */
11217/* Serial Peripheral Interface */
11218/* */
11219/******************************************************************************/
11220#define SPI_I2S_FULLDUPLEX_SUPPORT
11221#define I2S_APB1_APB2_FEATURE
11222
11223/******************* Bit definition for SPI_CR1 register ********************/
11224#define SPI_CR1_CPHA_Pos (0U)
11225#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11226#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11227#define SPI_CR1_CPOL_Pos (1U)
11228#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11229#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11230#define SPI_CR1_MSTR_Pos (2U)
11231#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11232#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11233
11234#define SPI_CR1_BR_Pos (3U)
11235#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11236#define SPI_CR1_BR SPI_CR1_BR_Msk
11237#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11238#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11239#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11240
11241#define SPI_CR1_SPE_Pos (6U)
11242#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11243#define SPI_CR1_SPE SPI_CR1_SPE_Msk
11244#define SPI_CR1_LSBFIRST_Pos (7U)
11245#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11246#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11247#define SPI_CR1_SSI_Pos (8U)
11248#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11249#define SPI_CR1_SSI SPI_CR1_SSI_Msk
11250#define SPI_CR1_SSM_Pos (9U)
11251#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11252#define SPI_CR1_SSM SPI_CR1_SSM_Msk
11253#define SPI_CR1_RXONLY_Pos (10U)
11254#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11255#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11256#define SPI_CR1_DFF_Pos (11U)
11257#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
11258#define SPI_CR1_DFF SPI_CR1_DFF_Msk
11259#define SPI_CR1_CRCNEXT_Pos (12U)
11260#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11261#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11262#define SPI_CR1_CRCEN_Pos (13U)
11263#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11264#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11265#define SPI_CR1_BIDIOE_Pos (14U)
11266#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11267#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11268#define SPI_CR1_BIDIMODE_Pos (15U)
11269#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11270#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11271
11272/******************* Bit definition for SPI_CR2 register ********************/
11273#define SPI_CR2_RXDMAEN_Pos (0U)
11274#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11275#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11276#define SPI_CR2_TXDMAEN_Pos (1U)
11277#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11278#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11279#define SPI_CR2_SSOE_Pos (2U)
11280#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11281#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11282#define SPI_CR2_FRF_Pos (4U)
11283#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11284#define SPI_CR2_FRF SPI_CR2_FRF_Msk
11285#define SPI_CR2_ERRIE_Pos (5U)
11286#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11287#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11288#define SPI_CR2_RXNEIE_Pos (6U)
11289#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11290#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11291#define SPI_CR2_TXEIE_Pos (7U)
11292#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11293#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11294
11295/******************** Bit definition for SPI_SR register ********************/
11296#define SPI_SR_RXNE_Pos (0U)
11297#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11298#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11299#define SPI_SR_TXE_Pos (1U)
11300#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11301#define SPI_SR_TXE SPI_SR_TXE_Msk
11302#define SPI_SR_CHSIDE_Pos (2U)
11303#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11304#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11305#define SPI_SR_UDR_Pos (3U)
11306#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11307#define SPI_SR_UDR SPI_SR_UDR_Msk
11308#define SPI_SR_CRCERR_Pos (4U)
11309#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11310#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11311#define SPI_SR_MODF_Pos (5U)
11312#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11313#define SPI_SR_MODF SPI_SR_MODF_Msk
11314#define SPI_SR_OVR_Pos (6U)
11315#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11316#define SPI_SR_OVR SPI_SR_OVR_Msk
11317#define SPI_SR_BSY_Pos (7U)
11318#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11319#define SPI_SR_BSY SPI_SR_BSY_Msk
11320#define SPI_SR_FRE_Pos (8U)
11321#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11322#define SPI_SR_FRE SPI_SR_FRE_Msk
11323
11324/******************** Bit definition for SPI_DR register ********************/
11325#define SPI_DR_DR_Pos (0U)
11326#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11327#define SPI_DR_DR SPI_DR_DR_Msk
11328
11329/******************* Bit definition for SPI_CRCPR register ******************/
11330#define SPI_CRCPR_CRCPOLY_Pos (0U)
11331#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11332#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11333
11334/****************** Bit definition for SPI_RXCRCR register ******************/
11335#define SPI_RXCRCR_RXCRC_Pos (0U)
11336#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11337#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11338
11339/****************** Bit definition for SPI_TXCRCR register ******************/
11340#define SPI_TXCRCR_TXCRC_Pos (0U)
11341#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11342#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11343
11344/****************** Bit definition for SPI_I2SCFGR register *****************/
11345#define SPI_I2SCFGR_CHLEN_Pos (0U)
11346#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11347#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11348
11349#define SPI_I2SCFGR_DATLEN_Pos (1U)
11350#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11351#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11352#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11353#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11354
11355#define SPI_I2SCFGR_CKPOL_Pos (3U)
11356#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11357#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11358
11359#define SPI_I2SCFGR_I2SSTD_Pos (4U)
11360#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11361#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11362#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11363#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11364
11365#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11366#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11367#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
11368
11369#define SPI_I2SCFGR_I2SCFG_Pos (8U)
11370#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
11371#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
11372#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
11373#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
11374
11375#define SPI_I2SCFGR_I2SE_Pos (10U)
11376#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
11377#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
11378#define SPI_I2SCFGR_I2SMOD_Pos (11U)
11379#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
11380#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
11381#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
11382#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
11383#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
11384
11385/****************** Bit definition for SPI_I2SPR register *******************/
11386#define SPI_I2SPR_I2SDIV_Pos (0U)
11387#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
11388#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
11389#define SPI_I2SPR_ODD_Pos (8U)
11390#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
11391#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
11392#define SPI_I2SPR_MCKOE_Pos (9U)
11393#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
11394#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
11395
11396/******************************************************************************/
11397/* */
11398/* SYSCFG */
11399/* */
11400/******************************************************************************/
11401/****************** Bit definition for SYSCFG_MEMRMP register ***************/
11402#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11403#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11404#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
11405#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11406#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11407/****************** Bit definition for SYSCFG_PMC register ******************/
11408#define SYSCFG_PMC_ADC1DC2_Pos (16U)
11409#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
11410#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
11411
11412/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11413#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11414#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
11415#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
11416#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11417#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
11418#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
11419#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11420#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
11421#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
11422#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11423#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
11424#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
11428#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
11429#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
11430#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
11431#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
11432#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
11433#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
11434#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
11435#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
11436
11440#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
11441#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
11442#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
11443#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
11444#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
11445#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
11446#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
11447#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
11448
11452#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
11453#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
11454#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
11455#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
11456#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
11457#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
11458#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
11459#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
11460
11464#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
11465#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
11466#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
11467#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
11468#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
11469#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
11470#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
11471#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
11472
11473/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11474#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11475#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
11476#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
11477#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11478#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
11479#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
11480#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11481#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
11482#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
11483#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11484#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
11485#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
11486
11490#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
11491#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
11492#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
11493#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
11494#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
11495#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
11496#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
11497#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
11498
11502#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
11503#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
11504#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
11505#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
11506#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
11507#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
11508#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
11509#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
11510
11514#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
11515#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
11516#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
11517#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
11518#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
11519#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
11520#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
11521#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
11522
11526#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
11527#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
11528#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
11529#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
11530#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
11531#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
11532#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
11533#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
11534
11535/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11536#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11537#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
11538#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
11539#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11540#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
11541#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
11542#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11543#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
11544#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
11545#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11546#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
11547#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
11548
11552#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
11553#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
11554#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
11555#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
11556#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
11557#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
11558#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
11559#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
11560
11564#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
11565#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
11566#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
11567#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
11568#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
11569#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
11570#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
11571#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
11572
11576#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
11577#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
11578#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
11579#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
11580#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
11581#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
11582#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
11583#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
11584
11588#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
11589#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
11590#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
11591#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
11592#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
11593#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
11594#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
11595#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
11596
11597/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11598#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11599#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
11600#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
11601#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11602#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
11603#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
11604#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11605#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
11606#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
11607#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11608#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
11609#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
11610
11614#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
11615#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
11616#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
11617#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
11618#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
11619#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
11620#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
11621#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
11622
11626#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
11627#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
11628#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
11629#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
11630#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
11631#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
11632#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
11633#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
11634
11638#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
11639#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
11640#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
11641#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
11642#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
11643#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
11644#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
11645#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
11646
11650#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
11651#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
11652#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
11653#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
11654#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
11655#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
11656#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
11657#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
11658
11659/****************** Bit definition for SYSCFG_CMPCR register ****************/
11660#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11661#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
11662#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
11663#define SYSCFG_CMPCR_READY_Pos (8U)
11664#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
11665#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
11666/****************** Bit definition for SYSCFG_CFGR register ****************/
11667#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
11668#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos)
11669#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk
11670#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
11671#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos)
11672#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk
11673
11674
11675/******************************************************************************/
11676/* */
11677/* TIM */
11678/* */
11679/******************************************************************************/
11680/******************* Bit definition for TIM_CR1 register ********************/
11681#define TIM_CR1_CEN_Pos (0U)
11682#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
11683#define TIM_CR1_CEN TIM_CR1_CEN_Msk
11684#define TIM_CR1_UDIS_Pos (1U)
11685#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
11686#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
11687#define TIM_CR1_URS_Pos (2U)
11688#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
11689#define TIM_CR1_URS TIM_CR1_URS_Msk
11690#define TIM_CR1_OPM_Pos (3U)
11691#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
11692#define TIM_CR1_OPM TIM_CR1_OPM_Msk
11693#define TIM_CR1_DIR_Pos (4U)
11694#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
11695#define TIM_CR1_DIR TIM_CR1_DIR_Msk
11696
11697#define TIM_CR1_CMS_Pos (5U)
11698#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
11699#define TIM_CR1_CMS TIM_CR1_CMS_Msk
11700#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
11701#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
11702
11703#define TIM_CR1_ARPE_Pos (7U)
11704#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
11705#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
11706
11707#define TIM_CR1_CKD_Pos (8U)
11708#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
11709#define TIM_CR1_CKD TIM_CR1_CKD_Msk
11710#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
11711#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
11712
11713/******************* Bit definition for TIM_CR2 register ********************/
11714#define TIM_CR2_CCPC_Pos (0U)
11715#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
11716#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
11717#define TIM_CR2_CCUS_Pos (2U)
11718#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
11719#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
11720#define TIM_CR2_CCDS_Pos (3U)
11721#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
11722#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
11723
11724#define TIM_CR2_MMS_Pos (4U)
11725#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
11726#define TIM_CR2_MMS TIM_CR2_MMS_Msk
11727#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
11728#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
11729#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
11730
11731#define TIM_CR2_TI1S_Pos (7U)
11732#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
11733#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
11734#define TIM_CR2_OIS1_Pos (8U)
11735#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
11736#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
11737#define TIM_CR2_OIS1N_Pos (9U)
11738#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
11739#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
11740#define TIM_CR2_OIS2_Pos (10U)
11741#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
11742#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
11743#define TIM_CR2_OIS2N_Pos (11U)
11744#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
11745#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
11746#define TIM_CR2_OIS3_Pos (12U)
11747#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
11748#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
11749#define TIM_CR2_OIS3N_Pos (13U)
11750#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
11751#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
11752#define TIM_CR2_OIS4_Pos (14U)
11753#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
11754#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
11755
11756/******************* Bit definition for TIM_SMCR register *******************/
11757#define TIM_SMCR_SMS_Pos (0U)
11758#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
11759#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
11760#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
11761#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
11762#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
11763
11764#define TIM_SMCR_TS_Pos (4U)
11765#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
11766#define TIM_SMCR_TS TIM_SMCR_TS_Msk
11767#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
11768#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
11769#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
11770
11771#define TIM_SMCR_MSM_Pos (7U)
11772#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
11773#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
11774
11775#define TIM_SMCR_ETF_Pos (8U)
11776#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
11777#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
11778#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
11779#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
11780#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
11781#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
11782
11783#define TIM_SMCR_ETPS_Pos (12U)
11784#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
11785#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
11786#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
11787#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
11788
11789#define TIM_SMCR_ECE_Pos (14U)
11790#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
11791#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
11792#define TIM_SMCR_ETP_Pos (15U)
11793#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
11794#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
11795
11796/******************* Bit definition for TIM_DIER register *******************/
11797#define TIM_DIER_UIE_Pos (0U)
11798#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
11799#define TIM_DIER_UIE TIM_DIER_UIE_Msk
11800#define TIM_DIER_CC1IE_Pos (1U)
11801#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
11802#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
11803#define TIM_DIER_CC2IE_Pos (2U)
11804#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
11805#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
11806#define TIM_DIER_CC3IE_Pos (3U)
11807#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
11808#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
11809#define TIM_DIER_CC4IE_Pos (4U)
11810#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
11811#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
11812#define TIM_DIER_COMIE_Pos (5U)
11813#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
11814#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
11815#define TIM_DIER_TIE_Pos (6U)
11816#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
11817#define TIM_DIER_TIE TIM_DIER_TIE_Msk
11818#define TIM_DIER_BIE_Pos (7U)
11819#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
11820#define TIM_DIER_BIE TIM_DIER_BIE_Msk
11821#define TIM_DIER_UDE_Pos (8U)
11822#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
11823#define TIM_DIER_UDE TIM_DIER_UDE_Msk
11824#define TIM_DIER_CC1DE_Pos (9U)
11825#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
11826#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
11827#define TIM_DIER_CC2DE_Pos (10U)
11828#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
11829#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
11830#define TIM_DIER_CC3DE_Pos (11U)
11831#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
11832#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
11833#define TIM_DIER_CC4DE_Pos (12U)
11834#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
11835#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
11836#define TIM_DIER_COMDE_Pos (13U)
11837#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
11838#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
11839#define TIM_DIER_TDE_Pos (14U)
11840#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
11841#define TIM_DIER_TDE TIM_DIER_TDE_Msk
11842
11843/******************** Bit definition for TIM_SR register ********************/
11844#define TIM_SR_UIF_Pos (0U)
11845#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
11846#define TIM_SR_UIF TIM_SR_UIF_Msk
11847#define TIM_SR_CC1IF_Pos (1U)
11848#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
11849#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
11850#define TIM_SR_CC2IF_Pos (2U)
11851#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
11852#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
11853#define TIM_SR_CC3IF_Pos (3U)
11854#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
11855#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
11856#define TIM_SR_CC4IF_Pos (4U)
11857#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
11858#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
11859#define TIM_SR_COMIF_Pos (5U)
11860#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
11861#define TIM_SR_COMIF TIM_SR_COMIF_Msk
11862#define TIM_SR_TIF_Pos (6U)
11863#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
11864#define TIM_SR_TIF TIM_SR_TIF_Msk
11865#define TIM_SR_BIF_Pos (7U)
11866#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
11867#define TIM_SR_BIF TIM_SR_BIF_Msk
11868#define TIM_SR_CC1OF_Pos (9U)
11869#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
11870#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
11871#define TIM_SR_CC2OF_Pos (10U)
11872#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
11873#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
11874#define TIM_SR_CC3OF_Pos (11U)
11875#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
11876#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
11877#define TIM_SR_CC4OF_Pos (12U)
11878#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
11879#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
11880
11881/******************* Bit definition for TIM_EGR register ********************/
11882#define TIM_EGR_UG_Pos (0U)
11883#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
11884#define TIM_EGR_UG TIM_EGR_UG_Msk
11885#define TIM_EGR_CC1G_Pos (1U)
11886#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
11887#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
11888#define TIM_EGR_CC2G_Pos (2U)
11889#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
11890#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
11891#define TIM_EGR_CC3G_Pos (3U)
11892#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
11893#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
11894#define TIM_EGR_CC4G_Pos (4U)
11895#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
11896#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
11897#define TIM_EGR_COMG_Pos (5U)
11898#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
11899#define TIM_EGR_COMG TIM_EGR_COMG_Msk
11900#define TIM_EGR_TG_Pos (6U)
11901#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
11902#define TIM_EGR_TG TIM_EGR_TG_Msk
11903#define TIM_EGR_BG_Pos (7U)
11904#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
11905#define TIM_EGR_BG TIM_EGR_BG_Msk
11906
11907/****************** Bit definition for TIM_CCMR1 register *******************/
11908#define TIM_CCMR1_CC1S_Pos (0U)
11909#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
11910#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
11911#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
11912#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
11913
11914#define TIM_CCMR1_OC1FE_Pos (2U)
11915#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
11916#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
11917#define TIM_CCMR1_OC1PE_Pos (3U)
11918#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
11919#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
11920
11921#define TIM_CCMR1_OC1M_Pos (4U)
11922#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
11923#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
11924#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
11925#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
11926#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
11927
11928#define TIM_CCMR1_OC1CE_Pos (7U)
11929#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
11930#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
11931
11932#define TIM_CCMR1_CC2S_Pos (8U)
11933#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
11934#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
11935#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
11936#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
11937
11938#define TIM_CCMR1_OC2FE_Pos (10U)
11939#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
11940#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
11941#define TIM_CCMR1_OC2PE_Pos (11U)
11942#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
11943#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
11944
11945#define TIM_CCMR1_OC2M_Pos (12U)
11946#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
11947#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
11948#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
11949#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
11950#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
11951
11952#define TIM_CCMR1_OC2CE_Pos (15U)
11953#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
11954#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
11955
11956/*----------------------------------------------------------------------------*/
11957
11958#define TIM_CCMR1_IC1PSC_Pos (2U)
11959#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
11960#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
11961#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
11962#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
11963
11964#define TIM_CCMR1_IC1F_Pos (4U)
11965#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
11966#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
11967#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
11968#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
11969#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
11970#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
11971
11972#define TIM_CCMR1_IC2PSC_Pos (10U)
11973#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
11974#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
11975#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
11976#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
11977
11978#define TIM_CCMR1_IC2F_Pos (12U)
11979#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
11980#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
11981#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
11982#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
11983#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
11984#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
11985
11986/****************** Bit definition for TIM_CCMR2 register *******************/
11987#define TIM_CCMR2_CC3S_Pos (0U)
11988#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
11989#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
11990#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
11991#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
11992
11993#define TIM_CCMR2_OC3FE_Pos (2U)
11994#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
11995#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
11996#define TIM_CCMR2_OC3PE_Pos (3U)
11997#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
11998#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
11999
12000#define TIM_CCMR2_OC3M_Pos (4U)
12001#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
12002#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12003#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
12004#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
12005#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
12006
12007#define TIM_CCMR2_OC3CE_Pos (7U)
12008#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12009#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12010
12011#define TIM_CCMR2_CC4S_Pos (8U)
12012#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12013#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12014#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12015#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12016
12017#define TIM_CCMR2_OC4FE_Pos (10U)
12018#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12019#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12020#define TIM_CCMR2_OC4PE_Pos (11U)
12021#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12022#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12023
12024#define TIM_CCMR2_OC4M_Pos (12U)
12025#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
12026#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12027#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
12028#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
12029#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
12030
12031#define TIM_CCMR2_OC4CE_Pos (15U)
12032#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12033#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12034
12035/*----------------------------------------------------------------------------*/
12036
12037#define TIM_CCMR2_IC3PSC_Pos (2U)
12038#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12039#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12040#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12041#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12042
12043#define TIM_CCMR2_IC3F_Pos (4U)
12044#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12045#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12046#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12047#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12048#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12049#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12050
12051#define TIM_CCMR2_IC4PSC_Pos (10U)
12052#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12053#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12054#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12055#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12056
12057#define TIM_CCMR2_IC4F_Pos (12U)
12058#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12059#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12060#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12061#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12062#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12063#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12064
12065/******************* Bit definition for TIM_CCER register *******************/
12066#define TIM_CCER_CC1E_Pos (0U)
12067#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12068#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12069#define TIM_CCER_CC1P_Pos (1U)
12070#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12071#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12072#define TIM_CCER_CC1NE_Pos (2U)
12073#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12074#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12075#define TIM_CCER_CC1NP_Pos (3U)
12076#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12077#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12078#define TIM_CCER_CC2E_Pos (4U)
12079#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12080#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12081#define TIM_CCER_CC2P_Pos (5U)
12082#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12083#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12084#define TIM_CCER_CC2NE_Pos (6U)
12085#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12086#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12087#define TIM_CCER_CC2NP_Pos (7U)
12088#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12089#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12090#define TIM_CCER_CC3E_Pos (8U)
12091#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12092#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12093#define TIM_CCER_CC3P_Pos (9U)
12094#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12095#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12096#define TIM_CCER_CC3NE_Pos (10U)
12097#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12098#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12099#define TIM_CCER_CC3NP_Pos (11U)
12100#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12101#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12102#define TIM_CCER_CC4E_Pos (12U)
12103#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12104#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12105#define TIM_CCER_CC4P_Pos (13U)
12106#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12107#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12108#define TIM_CCER_CC4NP_Pos (15U)
12109#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12110#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12111
12112/******************* Bit definition for TIM_CNT register ********************/
12113#define TIM_CNT_CNT_Pos (0U)
12114#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12115#define TIM_CNT_CNT TIM_CNT_CNT_Msk
12116
12117/******************* Bit definition for TIM_PSC register ********************/
12118#define TIM_PSC_PSC_Pos (0U)
12119#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12120#define TIM_PSC_PSC TIM_PSC_PSC_Msk
12121
12122/******************* Bit definition for TIM_ARR register ********************/
12123#define TIM_ARR_ARR_Pos (0U)
12124#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12125#define TIM_ARR_ARR TIM_ARR_ARR_Msk
12126
12127/******************* Bit definition for TIM_RCR register ********************/
12128#define TIM_RCR_REP_Pos (0U)
12129#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
12130#define TIM_RCR_REP TIM_RCR_REP_Msk
12131
12132/******************* Bit definition for TIM_CCR1 register *******************/
12133#define TIM_CCR1_CCR1_Pos (0U)
12134#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12135#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12136
12137/******************* Bit definition for TIM_CCR2 register *******************/
12138#define TIM_CCR2_CCR2_Pos (0U)
12139#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12140#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12141
12142/******************* Bit definition for TIM_CCR3 register *******************/
12143#define TIM_CCR3_CCR3_Pos (0U)
12144#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12145#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12146
12147/******************* Bit definition for TIM_CCR4 register *******************/
12148#define TIM_CCR4_CCR4_Pos (0U)
12149#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12150#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12151
12152/******************* Bit definition for TIM_BDTR register *******************/
12153#define TIM_BDTR_DTG_Pos (0U)
12154#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12155#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12156#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12157#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12158#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12159#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12160#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12161#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12162#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12163#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12164
12165#define TIM_BDTR_LOCK_Pos (8U)
12166#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12167#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12168#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12169#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12170
12171#define TIM_BDTR_OSSI_Pos (10U)
12172#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12173#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12174#define TIM_BDTR_OSSR_Pos (11U)
12175#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12176#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12177#define TIM_BDTR_BKE_Pos (12U)
12178#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12179#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12180#define TIM_BDTR_BKP_Pos (13U)
12181#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12182#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12183#define TIM_BDTR_AOE_Pos (14U)
12184#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12185#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12186#define TIM_BDTR_MOE_Pos (15U)
12187#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12188#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12189
12190/******************* Bit definition for TIM_DCR register ********************/
12191#define TIM_DCR_DBA_Pos (0U)
12192#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12193#define TIM_DCR_DBA TIM_DCR_DBA_Msk
12194#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12195#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12196#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12197#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12198#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12199
12200#define TIM_DCR_DBL_Pos (8U)
12201#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12202#define TIM_DCR_DBL TIM_DCR_DBL_Msk
12203#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12204#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12205#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12206#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12207#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12208
12209/******************* Bit definition for TIM_DMAR register *******************/
12210#define TIM_DMAR_DMAB_Pos (0U)
12211#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12212#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12213
12214/******************* Bit definition for TIM_OR register *********************/
12215#define TIM_OR_TI1_RMP_Pos (0U)
12216#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
12217#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
12218#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
12219#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
12220
12221#define TIM_OR_TI4_RMP_Pos (6U)
12222#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
12223#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
12224#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
12225#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
12226#define TIM_OR_ITR1_RMP_Pos (10U)
12227#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
12228#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
12229#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
12230#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
12231
12232
12233/******************************************************************************/
12234/* */
12235/* Universal Synchronous Asynchronous Receiver Transmitter */
12236/* */
12237/******************************************************************************/
12238/******************* Bit definition for USART_SR register *******************/
12239#define USART_SR_PE_Pos (0U)
12240#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
12241#define USART_SR_PE USART_SR_PE_Msk
12242#define USART_SR_FE_Pos (1U)
12243#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
12244#define USART_SR_FE USART_SR_FE_Msk
12245#define USART_SR_NE_Pos (2U)
12246#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
12247#define USART_SR_NE USART_SR_NE_Msk
12248#define USART_SR_ORE_Pos (3U)
12249#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
12250#define USART_SR_ORE USART_SR_ORE_Msk
12251#define USART_SR_IDLE_Pos (4U)
12252#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
12253#define USART_SR_IDLE USART_SR_IDLE_Msk
12254#define USART_SR_RXNE_Pos (5U)
12255#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
12256#define USART_SR_RXNE USART_SR_RXNE_Msk
12257#define USART_SR_TC_Pos (6U)
12258#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
12259#define USART_SR_TC USART_SR_TC_Msk
12260#define USART_SR_TXE_Pos (7U)
12261#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
12262#define USART_SR_TXE USART_SR_TXE_Msk
12263#define USART_SR_LBD_Pos (8U)
12264#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
12265#define USART_SR_LBD USART_SR_LBD_Msk
12266#define USART_SR_CTS_Pos (9U)
12267#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
12268#define USART_SR_CTS USART_SR_CTS_Msk
12269
12270/******************* Bit definition for USART_DR register *******************/
12271#define USART_DR_DR_Pos (0U)
12272#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
12273#define USART_DR_DR USART_DR_DR_Msk
12274
12275/****************** Bit definition for USART_BRR register *******************/
12276#define USART_BRR_DIV_Fraction_Pos (0U)
12277#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
12278#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
12279#define USART_BRR_DIV_Mantissa_Pos (4U)
12280#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
12281#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
12282
12283/****************** Bit definition for USART_CR1 register *******************/
12284#define USART_CR1_SBK_Pos (0U)
12285#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
12286#define USART_CR1_SBK USART_CR1_SBK_Msk
12287#define USART_CR1_RWU_Pos (1U)
12288#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
12289#define USART_CR1_RWU USART_CR1_RWU_Msk
12290#define USART_CR1_RE_Pos (2U)
12291#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
12292#define USART_CR1_RE USART_CR1_RE_Msk
12293#define USART_CR1_TE_Pos (3U)
12294#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
12295#define USART_CR1_TE USART_CR1_TE_Msk
12296#define USART_CR1_IDLEIE_Pos (4U)
12297#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
12298#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
12299#define USART_CR1_RXNEIE_Pos (5U)
12300#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
12301#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
12302#define USART_CR1_TCIE_Pos (6U)
12303#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
12304#define USART_CR1_TCIE USART_CR1_TCIE_Msk
12305#define USART_CR1_TXEIE_Pos (7U)
12306#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
12307#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
12308#define USART_CR1_PEIE_Pos (8U)
12309#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
12310#define USART_CR1_PEIE USART_CR1_PEIE_Msk
12311#define USART_CR1_PS_Pos (9U)
12312#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
12313#define USART_CR1_PS USART_CR1_PS_Msk
12314#define USART_CR1_PCE_Pos (10U)
12315#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
12316#define USART_CR1_PCE USART_CR1_PCE_Msk
12317#define USART_CR1_WAKE_Pos (11U)
12318#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
12319#define USART_CR1_WAKE USART_CR1_WAKE_Msk
12320#define USART_CR1_M_Pos (12U)
12321#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
12322#define USART_CR1_M USART_CR1_M_Msk
12323#define USART_CR1_UE_Pos (13U)
12324#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
12325#define USART_CR1_UE USART_CR1_UE_Msk
12326#define USART_CR1_OVER8_Pos (15U)
12327#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
12328#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
12329
12330/****************** Bit definition for USART_CR2 register *******************/
12331#define USART_CR2_ADD_Pos (0U)
12332#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
12333#define USART_CR2_ADD USART_CR2_ADD_Msk
12334#define USART_CR2_LBDL_Pos (5U)
12335#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
12336#define USART_CR2_LBDL USART_CR2_LBDL_Msk
12337#define USART_CR2_LBDIE_Pos (6U)
12338#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
12339#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
12340#define USART_CR2_LBCL_Pos (8U)
12341#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
12342#define USART_CR2_LBCL USART_CR2_LBCL_Msk
12343#define USART_CR2_CPHA_Pos (9U)
12344#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
12345#define USART_CR2_CPHA USART_CR2_CPHA_Msk
12346#define USART_CR2_CPOL_Pos (10U)
12347#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
12348#define USART_CR2_CPOL USART_CR2_CPOL_Msk
12349#define USART_CR2_CLKEN_Pos (11U)
12350#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
12351#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
12352
12353#define USART_CR2_STOP_Pos (12U)
12354#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
12355#define USART_CR2_STOP USART_CR2_STOP_Msk
12356#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
12357#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
12358
12359#define USART_CR2_LINEN_Pos (14U)
12360#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
12361#define USART_CR2_LINEN USART_CR2_LINEN_Msk
12362
12363/****************** Bit definition for USART_CR3 register *******************/
12364#define USART_CR3_EIE_Pos (0U)
12365#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
12366#define USART_CR3_EIE USART_CR3_EIE_Msk
12367#define USART_CR3_IREN_Pos (1U)
12368#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
12369#define USART_CR3_IREN USART_CR3_IREN_Msk
12370#define USART_CR3_IRLP_Pos (2U)
12371#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
12372#define USART_CR3_IRLP USART_CR3_IRLP_Msk
12373#define USART_CR3_HDSEL_Pos (3U)
12374#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
12375#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
12376#define USART_CR3_NACK_Pos (4U)
12377#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
12378#define USART_CR3_NACK USART_CR3_NACK_Msk
12379#define USART_CR3_SCEN_Pos (5U)
12380#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
12381#define USART_CR3_SCEN USART_CR3_SCEN_Msk
12382#define USART_CR3_DMAR_Pos (6U)
12383#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
12384#define USART_CR3_DMAR USART_CR3_DMAR_Msk
12385#define USART_CR3_DMAT_Pos (7U)
12386#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
12387#define USART_CR3_DMAT USART_CR3_DMAT_Msk
12388#define USART_CR3_RTSE_Pos (8U)
12389#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
12390#define USART_CR3_RTSE USART_CR3_RTSE_Msk
12391#define USART_CR3_CTSE_Pos (9U)
12392#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
12393#define USART_CR3_CTSE USART_CR3_CTSE_Msk
12394#define USART_CR3_CTSIE_Pos (10U)
12395#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
12396#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
12397#define USART_CR3_ONEBIT_Pos (11U)
12398#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
12399#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
12400
12401/****************** Bit definition for USART_GTPR register ******************/
12402#define USART_GTPR_PSC_Pos (0U)
12403#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
12404#define USART_GTPR_PSC USART_GTPR_PSC_Msk
12405#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
12406#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
12407#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
12408#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
12409#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
12410#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
12411#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
12412#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
12413
12414#define USART_GTPR_GT_Pos (8U)
12415#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
12416#define USART_GTPR_GT USART_GTPR_GT_Msk
12417
12418/******************************************************************************/
12419/* */
12420/* Window WATCHDOG */
12421/* */
12422/******************************************************************************/
12423/******************* Bit definition for WWDG_CR register ********************/
12424#define WWDG_CR_T_Pos (0U)
12425#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
12426#define WWDG_CR_T WWDG_CR_T_Msk
12427#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
12428#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
12429#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
12430#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
12431#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
12432#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
12433#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
12434/* Legacy defines */
12435#define WWDG_CR_T0 WWDG_CR_T_0
12436#define WWDG_CR_T1 WWDG_CR_T_1
12437#define WWDG_CR_T2 WWDG_CR_T_2
12438#define WWDG_CR_T3 WWDG_CR_T_3
12439#define WWDG_CR_T4 WWDG_CR_T_4
12440#define WWDG_CR_T5 WWDG_CR_T_5
12441#define WWDG_CR_T6 WWDG_CR_T_6
12442
12443#define WWDG_CR_WDGA_Pos (7U)
12444#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
12445#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
12446
12447/******************* Bit definition for WWDG_CFR register *******************/
12448#define WWDG_CFR_W_Pos (0U)
12449#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
12450#define WWDG_CFR_W WWDG_CFR_W_Msk
12451#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
12452#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
12453#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
12454#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
12455#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
12456#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
12457#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
12458/* Legacy defines */
12459#define WWDG_CFR_W0 WWDG_CFR_W_0
12460#define WWDG_CFR_W1 WWDG_CFR_W_1
12461#define WWDG_CFR_W2 WWDG_CFR_W_2
12462#define WWDG_CFR_W3 WWDG_CFR_W_3
12463#define WWDG_CFR_W4 WWDG_CFR_W_4
12464#define WWDG_CFR_W5 WWDG_CFR_W_5
12465#define WWDG_CFR_W6 WWDG_CFR_W_6
12466
12467#define WWDG_CFR_WDGTB_Pos (7U)
12468#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
12469#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
12470#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
12471#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
12472/* Legacy defines */
12473#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12474#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12475
12476#define WWDG_CFR_EWI_Pos (9U)
12477#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
12478#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
12479
12480/******************* Bit definition for WWDG_SR register ********************/
12481#define WWDG_SR_EWIF_Pos (0U)
12482#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
12483#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
12484
12485
12486/******************************************************************************/
12487/* */
12488/* DBG */
12489/* */
12490/******************************************************************************/
12491/******************** Bit definition for DBGMCU_IDCODE register *************/
12492#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12493#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
12494#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12495#define DBGMCU_IDCODE_REV_ID_Pos (16U)
12496#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
12497#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12498
12499/******************** Bit definition for DBGMCU_CR register *****************/
12500#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12501#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
12502#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12503#define DBGMCU_CR_DBG_STOP_Pos (1U)
12504#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
12505#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12506#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12507#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
12508#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12509#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12510#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
12511#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12512
12513#define DBGMCU_CR_TRACE_MODE_Pos (6U)
12514#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
12515#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12516#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
12517#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
12518
12519/******************** Bit definition for DBGMCU_APB1_FZ register ************/
12520#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12521#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
12522#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12523#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12524#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
12525#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12526#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12527#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
12528#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12529#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12530#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
12531#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12532#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12533#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
12534#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12535#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12536#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
12537#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12538#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12539#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
12540#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12541#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12542#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
12543#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12544#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12545#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
12546#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12547#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12548#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
12549#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12550#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12551#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
12552#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12553#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12554#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
12555#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12556#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12557#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
12558#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12559#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12560#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
12561#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12562#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12563#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
12564#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12565#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
12566#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
12567#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
12568#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12569#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
12570#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12571#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12572#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
12573#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12574
12575/******************** Bit definition for DBGMCU_APB2_FZ register ************/
12576#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12577#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
12578#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12579#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12580#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
12581#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12582#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12583#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
12584#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12585#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12586#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
12587#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12588#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12589#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
12590#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12591
12592/******************************************************************************/
12593/* */
12594/* USB_OTG */
12595/* */
12596/******************************************************************************/
12597/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
12598#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
12599#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
12600#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
12601#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
12602#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
12603#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
12604#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
12605#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
12606#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
12607#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
12608#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
12609#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
12610#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
12611#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
12612#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
12613#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
12614#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
12615#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
12616#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
12617#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
12618#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
12619#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
12620#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
12621#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
12622#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
12623#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
12624#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
12625#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
12626#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
12627#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
12628#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
12629#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
12630#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
12631#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
12632#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
12633#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
12634#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
12635#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
12636#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
12637#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
12638#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
12639#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
12640#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
12641#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
12642#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
12643#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
12644#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
12645#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
12646#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
12647#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
12648#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
12649#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
12650#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
12651#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
12652
12653/******************** Bit definition forUSB_OTG_HCFG register ********************/
12654
12655#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
12656#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
12657#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
12658#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
12659#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
12660#define USB_OTG_HCFG_FSLSS_Pos (2U)
12661#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
12662#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
12663
12664/******************** Bit definition for USB_OTG_DCFG register ********************/
12665
12666#define USB_OTG_DCFG_DSPD_Pos (0U)
12667#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
12668#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
12669#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
12670#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
12671#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
12672#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
12673#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
12674
12675#define USB_OTG_DCFG_DAD_Pos (4U)
12676#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
12677#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
12678#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
12679#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
12680#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
12681#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
12682#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
12683#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
12684#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
12685
12686#define USB_OTG_DCFG_PFIVL_Pos (11U)
12687#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
12688#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
12689#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
12690#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
12691
12692#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
12693#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
12694#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
12695
12696#define USB_OTG_DCFG_ERRATIM_Pos (15U)
12697#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
12698#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
12699
12700#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
12701#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
12702#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
12703#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
12704#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
12705
12706/******************** Bit definition for USB_OTG_PCGCR register ********************/
12707#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
12708#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
12709#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
12710#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
12711#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
12712#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
12713#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
12714#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
12715#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
12716
12717/******************** Bit definition for USB_OTG_GOTGINT register ********************/
12718#define USB_OTG_GOTGINT_SEDET_Pos (2U)
12719#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
12720#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
12721#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
12722#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
12723#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
12724#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
12725#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
12726#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
12727#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
12728#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
12729#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
12730#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
12731#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
12732#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
12733#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
12734#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
12735#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
12736#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
12737#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
12738#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
12739
12740/******************** Bit definition for USB_OTG_DCTL register ********************/
12741#define USB_OTG_DCTL_RWUSIG_Pos (0U)
12742#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
12743#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
12744#define USB_OTG_DCTL_SDIS_Pos (1U)
12745#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
12746#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
12747#define USB_OTG_DCTL_GINSTS_Pos (2U)
12748#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
12749#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
12750#define USB_OTG_DCTL_GONSTS_Pos (3U)
12751#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
12752#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
12753
12754#define USB_OTG_DCTL_TCTL_Pos (4U)
12755#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
12756#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
12757#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
12758#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
12759#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
12760#define USB_OTG_DCTL_SGINAK_Pos (7U)
12761#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
12762#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
12763#define USB_OTG_DCTL_CGINAK_Pos (8U)
12764#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
12765#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
12766#define USB_OTG_DCTL_SGONAK_Pos (9U)
12767#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
12768#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
12769#define USB_OTG_DCTL_CGONAK_Pos (10U)
12770#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
12771#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
12772#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
12773#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
12774#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
12775
12776/******************** Bit definition for USB_OTG_HFIR register ********************/
12777#define USB_OTG_HFIR_FRIVL_Pos (0U)
12778#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
12779#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
12780
12781/******************** Bit definition for USB_OTG_HFNUM register ********************/
12782#define USB_OTG_HFNUM_FRNUM_Pos (0U)
12783#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
12784#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
12785#define USB_OTG_HFNUM_FTREM_Pos (16U)
12786#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
12787#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
12788
12789/******************** Bit definition for USB_OTG_DSTS register ********************/
12790#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
12791#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
12792#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
12793
12794#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
12795#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
12796#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
12797#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
12798#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
12799#define USB_OTG_DSTS_EERR_Pos (3U)
12800#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
12801#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
12802#define USB_OTG_DSTS_FNSOF_Pos (8U)
12803#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
12804#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
12805
12806/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
12807#define USB_OTG_GAHBCFG_GINT_Pos (0U)
12808#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
12809#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
12810#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
12811#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12812#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
12813#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12814#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12815#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12816#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12817#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
12818#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
12819#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
12820#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
12821#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
12822#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
12823#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
12824#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
12825#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
12826#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
12827
12828/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
12829
12830#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
12831#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12832#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
12833#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12834#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12835#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
12836#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
12837#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
12838#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
12839#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
12840#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
12841#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
12842#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
12843#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
12844#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
12845#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
12846#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
12847#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
12848#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
12849#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
12850#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
12851#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
12852#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
12853#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
12854#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
12855#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
12856#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
12857#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
12858#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
12859#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
12860#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
12861#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
12862#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
12863#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
12864#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
12865#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
12866#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
12867#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
12868#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
12869#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
12870#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
12871#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
12872#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
12873#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
12874#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
12875#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
12876#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
12877#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
12878#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
12879#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
12880#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
12881#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
12882#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
12883#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
12884#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
12885#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
12886#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
12887#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
12888#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
12889#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
12890#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
12891
12892/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
12893#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
12894#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
12895#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
12896#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
12897#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
12898#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
12899#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
12900#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
12901#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
12902#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
12903#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
12904#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
12905#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
12906#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
12907#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
12908
12909
12910#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
12911#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12912#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
12913#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12914#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12915#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12916#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12917#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
12918#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
12919#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
12920#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
12921#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
12922#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
12923#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
12924
12925/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
12926#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
12927#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
12928#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
12929#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
12930#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
12931#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
12932#define USB_OTG_DIEPMSK_TOM_Pos (3U)
12933#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
12934#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
12935#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
12936#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
12937#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
12938#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
12939#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
12940#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
12941#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
12942#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
12943#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
12944#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
12945#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
12946#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
12947#define USB_OTG_DIEPMSK_NAKM_Pos (13U)
12948#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
12949#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
12950
12951/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
12952#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
12953#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
12954#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
12955#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
12956#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12957#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
12958#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12959#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12960#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12961#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12962#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12963#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12964#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12965#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
12966
12967#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
12968#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12969#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
12970#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12971#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12972#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12973#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12974#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12975#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12976#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12977#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
12978
12979/******************** Bit definition for USB_OTG_HAINT register ********************/
12980#define USB_OTG_HAINT_HAINT_Pos (0U)
12981#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
12982#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
12983
12984/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
12985#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
12986#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
12987#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
12988#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
12989#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
12990#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
12991#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
12992#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
12993#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
12994#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
12995#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
12996#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
12997#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
12998#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
12999#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
13000#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
13001#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
13002#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
13003#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13004#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
13005#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
13006#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13007#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
13008#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
13009#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13010#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
13011#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
13012#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
13013#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
13014#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
13015#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
13016#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
13017#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
13018#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
13019#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
13020#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
13021/******************** Bit definition for USB_OTG_GINTSTS register ********************/
13022#define USB_OTG_GINTSTS_CMOD_Pos (0U)
13023#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
13024#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
13025#define USB_OTG_GINTSTS_MMIS_Pos (1U)
13026#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
13027#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
13028#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13029#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
13030#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
13031#define USB_OTG_GINTSTS_SOF_Pos (3U)
13032#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
13033#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
13034#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13035#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
13036#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
13037#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13038#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
13039#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
13040#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13041#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
13042#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
13043#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13044#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
13045#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
13046#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13047#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
13048#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
13049#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13050#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
13051#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
13052#define USB_OTG_GINTSTS_USBRST_Pos (12U)
13053#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
13054#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
13055#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13056#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
13057#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
13058#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13059#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
13060#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
13061#define USB_OTG_GINTSTS_EOPF_Pos (15U)
13062#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
13063#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
13064#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13065#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
13066#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
13067#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13068#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
13069#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
13070#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13071#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
13072#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
13073#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13074#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
13075#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
13076#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13077#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
13078#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
13079#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
13080#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
13081#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
13082#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
13083#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
13084#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
13085#define USB_OTG_GINTSTS_HCINT_Pos (25U)
13086#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
13087#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
13088#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
13089#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
13090#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
13091#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
13092#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
13093#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
13094#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
13095#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
13096#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
13097#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
13098#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
13099#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
13100#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
13101#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
13102#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
13103#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
13104#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
13105#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
13106
13107/******************** Bit definition for USB_OTG_GINTMSK register ********************/
13108#define USB_OTG_GINTMSK_MMISM_Pos (1U)
13109#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
13110#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
13111#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
13112#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
13113#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
13114#define USB_OTG_GINTMSK_SOFM_Pos (3U)
13115#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
13116#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
13117#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
13118#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
13119#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
13120#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
13121#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
13122#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
13123#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
13124#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
13125#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
13126#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
13127#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
13128#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
13129#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
13130#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
13131#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
13132#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
13133#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
13134#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
13135#define USB_OTG_GINTMSK_USBRST_Pos (12U)
13136#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
13137#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
13138#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
13139#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
13140#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
13141#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
13142#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
13143#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
13144#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
13145#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
13146#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
13147#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
13148#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
13149#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
13150#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
13151#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
13152#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
13153#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
13154#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
13155#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
13156#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
13157#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
13158#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
13159#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
13160#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
13161#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
13162#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
13163#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
13164#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
13165#define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
13166#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos)
13167#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk
13168#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
13169#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
13170#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
13171#define USB_OTG_GINTMSK_HCIM_Pos (25U)
13172#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
13173#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
13174#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
13175#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
13176#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
13177#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
13178#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
13179#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
13180#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
13181#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
13182#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
13183#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
13184#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
13185#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
13186#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
13187#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
13188#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
13189#define USB_OTG_GINTMSK_WUIM_Pos (31U)
13190#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
13191#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
13192
13193/******************** Bit definition for USB_OTG_DAINT register ********************/
13194#define USB_OTG_DAINT_IEPINT_Pos (0U)
13195#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
13196#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
13197#define USB_OTG_DAINT_OEPINT_Pos (16U)
13198#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
13199#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
13200
13201/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
13202#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
13203#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
13204#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
13205
13206/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
13207#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
13208#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
13209#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
13210#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
13211#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
13212#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
13213#define USB_OTG_GRXSTSP_DPID_Pos (15U)
13214#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
13215#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
13216#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
13217#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
13218#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
13219
13220/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
13221#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
13222#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
13223#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
13224#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
13225#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
13226#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
13227
13228/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
13229#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
13230#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
13231#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
13232
13233/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
13234#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
13235#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
13236#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
13237
13238/******************** Bit definition for OTG register ********************/
13239#define USB_OTG_NPTXFSA_Pos (0U)
13240#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
13241#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
13242#define USB_OTG_NPTXFD_Pos (16U)
13243#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
13244#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
13245#define USB_OTG_TX0FSA_Pos (0U)
13246#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
13247#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
13248#define USB_OTG_TX0FD_Pos (16U)
13249#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
13250#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
13251
13252/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
13253#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
13254#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
13255#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
13256
13257/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
13258#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
13259#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
13260#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
13261
13262#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
13263#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13264#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
13265#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13266#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13267#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13268#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13269#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13270#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13271#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13272#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13273
13274#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
13275#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13276#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
13277#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13278#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13279#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13280#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13281#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13282#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13283#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13284
13285/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
13286#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
13287#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
13288#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
13289#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
13290#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
13291#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
13292
13293#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
13294#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13295#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
13296#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13297#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13298#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13299#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13300#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13301#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13302#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13303#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13304#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13305#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
13306#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
13307#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
13308
13309#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
13310#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13311#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
13312#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13313#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13314#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13315#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13316#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13317#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13318#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13319#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13320#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13321#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
13322#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
13323#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
13324
13325/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
13326#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
13327#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
13328#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
13329
13330/******************** Bit definition for USB_OTG_DEACHINT register ********************/
13331#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
13332#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
13333#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
13334#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
13335#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
13336#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
13337
13338/******************** Bit definition for USB_OTG_GCCFG register ********************/
13339#define USB_OTG_GCCFG_DCDET_Pos (0U)
13340#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
13341#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
13342#define USB_OTG_GCCFG_PDET_Pos (1U)
13343#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
13344#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
13345#define USB_OTG_GCCFG_SDET_Pos (2U)
13346#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
13347#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
13348#define USB_OTG_GCCFG_PS2DET_Pos (3U)
13349#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
13350#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
13351#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
13352#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
13353#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
13354#define USB_OTG_GCCFG_BCDEN_Pos (17U)
13355#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
13356#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
13357#define USB_OTG_GCCFG_DCDEN_Pos (18U)
13358#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
13359#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
13360#define USB_OTG_GCCFG_PDEN_Pos (19U)
13361#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
13362#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
13363#define USB_OTG_GCCFG_SDEN_Pos (20U)
13364#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
13365#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
13366#define USB_OTG_GCCFG_VBDEN_Pos (21U)
13367#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
13368#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
13369
13370/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
13371#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
13372#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
13373#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
13374#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
13375#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
13376#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
13377
13378/******************** Bit definition for USB_OTG_CID register ********************/
13379#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
13380#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
13381#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
13382
13383/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
13384#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
13385#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
13386#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
13387#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
13388#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
13389#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
13390#define USB_OTG_GLPMCFG_BESL_Pos (2U)
13391#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
13392#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
13393#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
13394#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
13395#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
13396#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
13397#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
13398#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
13399#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
13400#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
13401#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
13402#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
13403#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
13404#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
13405#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
13406#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
13407#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
13408#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
13409#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
13410#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
13411#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
13412#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
13413#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
13414#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
13415#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
13416#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
13417#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
13418#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
13419#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
13420#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
13421#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
13422#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
13423#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
13424#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
13425#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
13426#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
13427#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
13428#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
13429
13430/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
13431#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
13432#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
13433#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
13434#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
13435#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
13436#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
13437#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
13438#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
13439#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
13440#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
13441#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
13442#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
13443#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
13444#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
13445#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
13446#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
13447#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
13448#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
13449#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
13450#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
13451#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
13452#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
13453#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
13454#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
13455#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
13456#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
13457#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
13458
13459/******************** Bit definition for USB_OTG_HPRT register ********************/
13460#define USB_OTG_HPRT_PCSTS_Pos (0U)
13461#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
13462#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
13463#define USB_OTG_HPRT_PCDET_Pos (1U)
13464#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
13465#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
13466#define USB_OTG_HPRT_PENA_Pos (2U)
13467#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
13468#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
13469#define USB_OTG_HPRT_PENCHNG_Pos (3U)
13470#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
13471#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
13472#define USB_OTG_HPRT_POCA_Pos (4U)
13473#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
13474#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
13475#define USB_OTG_HPRT_POCCHNG_Pos (5U)
13476#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
13477#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
13478#define USB_OTG_HPRT_PRES_Pos (6U)
13479#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
13480#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
13481#define USB_OTG_HPRT_PSUSP_Pos (7U)
13482#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
13483#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
13484#define USB_OTG_HPRT_PRST_Pos (8U)
13485#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
13486#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
13487
13488#define USB_OTG_HPRT_PLSTS_Pos (10U)
13489#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
13490#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
13491#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
13492#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
13493#define USB_OTG_HPRT_PPWR_Pos (12U)
13494#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
13495#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
13496
13497#define USB_OTG_HPRT_PTCTL_Pos (13U)
13498#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
13499#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
13500#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
13501#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
13502#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
13503#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
13504
13505#define USB_OTG_HPRT_PSPD_Pos (17U)
13506#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
13507#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
13508#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
13509#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
13510
13511/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
13512#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
13513#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
13514#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
13515#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
13516#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
13517#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
13518#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
13519#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
13520#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
13521#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
13522#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
13523#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
13524#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
13525#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
13526#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
13527#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
13528#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
13529#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
13530#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
13531#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
13532#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
13533#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
13534#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
13535#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
13536#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
13537#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
13538#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
13539#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
13540#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
13541#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
13542#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
13543#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
13544#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
13545
13546/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
13547#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
13548#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
13549#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
13550#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
13551#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
13552#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
13553
13554/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
13555#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
13556#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
13557#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
13558#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
13559#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
13560#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
13561#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
13562#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
13563#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
13564#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
13565#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
13566#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
13567
13568#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
13569#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
13570#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
13571#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
13572#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
13573#define USB_OTG_DIEPCTL_STALL_Pos (21U)
13574#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
13575#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
13576
13577#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
13578#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13579#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
13580#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13581#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13582#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13583#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
13584#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
13585#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
13586#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
13587#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
13588#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
13589#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
13590#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
13591#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
13592#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
13593#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
13594#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
13595#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
13596#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
13597#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
13598#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
13599#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
13600#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
13601#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
13602
13603/******************** Bit definition for USB_OTG_HCCHAR register ********************/
13604#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
13605#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
13606#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
13607
13608#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
13609#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
13610#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
13611#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
13612#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
13613#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
13614#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
13615#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
13616#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
13617#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
13618#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
13619#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
13620#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
13621
13622#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
13623#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
13624#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
13625#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
13626#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
13627
13628#define USB_OTG_HCCHAR_MC_Pos (20U)
13629#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
13630#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
13631#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
13632#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
13633
13634#define USB_OTG_HCCHAR_DAD_Pos (22U)
13635#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
13636#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
13637#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
13638#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
13639#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
13640#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
13641#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
13642#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
13643#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
13644#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
13645#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
13646#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
13647#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
13648#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
13649#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
13650#define USB_OTG_HCCHAR_CHENA_Pos (31U)
13651#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
13652#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
13653
13654/******************** Bit definition for USB_OTG_HCSPLT register ********************/
13655
13656#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
13657#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
13658#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
13659#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13660#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13661#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13662#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13663#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13664#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13665#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
13666
13667#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
13668#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
13669#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
13670#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13671#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13672#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13673#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13674#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13675#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13676#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
13677
13678#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
13679#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
13680#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
13681#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
13682#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
13683#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
13684#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
13685#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
13686#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
13687#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
13688#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
13689
13690/******************** Bit definition for USB_OTG_HCINT register ********************/
13691#define USB_OTG_HCINT_XFRC_Pos (0U)
13692#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
13693#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
13694#define USB_OTG_HCINT_CHH_Pos (1U)
13695#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
13696#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
13697#define USB_OTG_HCINT_AHBERR_Pos (2U)
13698#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
13699#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
13700#define USB_OTG_HCINT_STALL_Pos (3U)
13701#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
13702#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
13703#define USB_OTG_HCINT_NAK_Pos (4U)
13704#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
13705#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
13706#define USB_OTG_HCINT_ACK_Pos (5U)
13707#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
13708#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
13709#define USB_OTG_HCINT_NYET_Pos (6U)
13710#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
13711#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
13712#define USB_OTG_HCINT_TXERR_Pos (7U)
13713#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
13714#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
13715#define USB_OTG_HCINT_BBERR_Pos (8U)
13716#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
13717#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
13718#define USB_OTG_HCINT_FRMOR_Pos (9U)
13719#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
13720#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
13721#define USB_OTG_HCINT_DTERR_Pos (10U)
13722#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
13723#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
13724
13725/******************** Bit definition for USB_OTG_DIEPINT register ********************/
13726#define USB_OTG_DIEPINT_XFRC_Pos (0U)
13727#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
13728#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
13729#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
13730#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
13731#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
13732#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
13733#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
13734#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
13735#define USB_OTG_DIEPINT_TOC_Pos (3U)
13736#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
13737#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
13738#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
13739#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
13740#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
13741#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
13742#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
13743#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
13744#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
13745#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
13746#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
13747#define USB_OTG_DIEPINT_TXFE_Pos (7U)
13748#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
13749#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
13750#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
13751#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
13752#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
13753#define USB_OTG_DIEPINT_BNA_Pos (9U)
13754#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
13755#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
13756#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
13757#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
13758#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
13759#define USB_OTG_DIEPINT_BERR_Pos (12U)
13760#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
13761#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
13762#define USB_OTG_DIEPINT_NAK_Pos (13U)
13763#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
13764#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
13765
13766/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
13767#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
13768#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
13769#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
13770#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
13771#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
13772#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
13773#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
13774#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
13775#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
13776#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
13777#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
13778#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
13779#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
13780#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
13781#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
13782#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
13783#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
13784#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
13785#define USB_OTG_HCINTMSK_NYET_Pos (6U)
13786#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
13787#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
13788#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
13789#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
13790#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
13791#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
13792#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
13793#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
13794#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
13795#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
13796#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
13797#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
13798#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
13799#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
13800
13801/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
13802
13803#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
13804#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
13805#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
13806#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
13807#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
13808#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
13809#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
13810#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
13811#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
13812/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
13813#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
13814#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
13815#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
13816#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
13817#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
13818#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
13819#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
13820#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
13821#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
13822#define USB_OTG_HCTSIZ_DPID_Pos (29U)
13823#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
13824#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
13825#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
13826#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
13827
13828/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
13829#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
13830#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
13831#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
13832
13833/******************** Bit definition for USB_OTG_HCDMA register ********************/
13834#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
13835#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
13836#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
13837
13838/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
13839#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
13840#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
13841#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
13842
13843/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
13844#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
13845#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
13846#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
13847#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
13848#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
13849#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
13850
13851/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
13852
13853#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
13854#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
13855#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
13856#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
13857#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
13858#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
13859#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
13860#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
13861#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
13862#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
13863#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
13864#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
13865#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
13866#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
13867#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
13868#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
13869#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
13870#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
13871#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
13872#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
13873#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
13874#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
13875#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
13876#define USB_OTG_DOEPCTL_STALL_Pos (21U)
13877#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
13878#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
13879#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
13880#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
13881#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
13882#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
13883#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
13884#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
13885#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
13886#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
13887#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
13888#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
13889#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
13890#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
13891
13892/******************** Bit definition for USB_OTG_DOEPINT register ********************/
13893#define USB_OTG_DOEPINT_XFRC_Pos (0U)
13894#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
13895#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
13896#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
13897#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
13898#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
13899#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
13900#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
13901#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
13902#define USB_OTG_DOEPINT_STUP_Pos (3U)
13903#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
13904#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
13905#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
13906#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
13907#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
13908#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
13909#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
13910#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
13911#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
13912#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
13913#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
13914#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
13915#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
13916#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
13917#define USB_OTG_DOEPINT_NAK_Pos (13U)
13918#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
13919#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
13920#define USB_OTG_DOEPINT_NYET_Pos (14U)
13921#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
13922#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
13923#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
13924#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
13925#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
13926/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
13927
13928#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
13929#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
13930#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
13931#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
13932#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
13933#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
13934
13935#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
13936#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
13937#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
13938#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
13939#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
13940
13941/******************** Bit definition for PCGCCTL register ********************/
13942#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
13943#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
13944#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
13945#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
13946#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
13947#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
13948#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
13949#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
13950#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
13951
13952/* Legacy define */
13953/******************** Bit definition for OTG register ********************/
13954#define USB_OTG_CHNUM_Pos (0U)
13955#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
13956#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
13957#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
13958#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
13959#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
13960#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
13961#define USB_OTG_BCNT_Pos (4U)
13962#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
13963#define USB_OTG_BCNT USB_OTG_BCNT_Msk
13964
13965#define USB_OTG_DPID_Pos (15U)
13966#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
13967#define USB_OTG_DPID USB_OTG_DPID_Msk
13968#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
13969#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
13970
13971#define USB_OTG_PKTSTS_Pos (17U)
13972#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
13973#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
13974#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
13975#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
13976#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
13977#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
13978
13979#define USB_OTG_EPNUM_Pos (0U)
13980#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
13981#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
13982#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
13983#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
13984#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
13985#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
13986
13987#define USB_OTG_FRMNUM_Pos (21U)
13988#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
13989#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
13990#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
13991#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
13992#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
13993#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
13997
14001
14005
14006/******************************* ADC Instances ********************************/
14007#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14008
14009#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
14010
14011/******************************* CAN Instances ********************************/
14012#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14013 ((INSTANCE) == CAN2))
14014
14015/****************************** DFSDM Instances *******************************/
14016#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
14017 ((INSTANCE) == DFSDM1_Filter1))
14018
14019#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
14020 ((INSTANCE) == DFSDM1_Channel1) || \
14021 ((INSTANCE) == DFSDM1_Channel2) || \
14022 ((INSTANCE) == DFSDM1_Channel3))
14023/******************************* CRC Instances ********************************/
14024#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14025
14026
14027/******************************** DMA Instances *******************************/
14028#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14029 ((INSTANCE) == DMA1_Stream1) || \
14030 ((INSTANCE) == DMA1_Stream2) || \
14031 ((INSTANCE) == DMA1_Stream3) || \
14032 ((INSTANCE) == DMA1_Stream4) || \
14033 ((INSTANCE) == DMA1_Stream5) || \
14034 ((INSTANCE) == DMA1_Stream6) || \
14035 ((INSTANCE) == DMA1_Stream7) || \
14036 ((INSTANCE) == DMA2_Stream0) || \
14037 ((INSTANCE) == DMA2_Stream1) || \
14038 ((INSTANCE) == DMA2_Stream2) || \
14039 ((INSTANCE) == DMA2_Stream3) || \
14040 ((INSTANCE) == DMA2_Stream4) || \
14041 ((INSTANCE) == DMA2_Stream5) || \
14042 ((INSTANCE) == DMA2_Stream6) || \
14043 ((INSTANCE) == DMA2_Stream7))
14044
14045/******************************* GPIO Instances *******************************/
14046#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14047 ((INSTANCE) == GPIOB) || \
14048 ((INSTANCE) == GPIOC) || \
14049 ((INSTANCE) == GPIOD) || \
14050 ((INSTANCE) == GPIOE) || \
14051 ((INSTANCE) == GPIOH))
14052
14053/******************************** I2C Instances *******************************/
14054#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14055 ((INSTANCE) == I2C2) || \
14056 ((INSTANCE) == I2C3))
14057
14058/******************************* SMBUS Instances ******************************/
14059#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
14060
14061/******************************** I2S Instances *******************************/
14062#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14063 ((INSTANCE) == SPI3))
14064
14065#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14066 ((INSTANCE) == SPI2) || \
14067 ((INSTANCE) == SPI3) || \
14068 ((INSTANCE) == SPI4) || \
14069 ((INSTANCE) == SPI5))
14070
14071/*************************** I2S Extended Instances ***************************/
14072#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
14073 ((INSTANCE) == I2S3ext))
14074/* Legacy Defines */
14075#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
14076
14077/******************************* RNG Instances ********************************/
14078#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
14079
14080/****************************** RTC Instances *********************************/
14081#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14082
14083
14084/******************************** SPI Instances *******************************/
14085
14086#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14087 ((INSTANCE) == SPI2) || \
14088 ((INSTANCE) == SPI3) || \
14089 ((INSTANCE) == SPI4) || \
14090 ((INSTANCE) == SPI5))
14091
14092
14093/****************** TIM Instances : All supported instances *******************/
14094#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14095 ((INSTANCE) == TIM2) || \
14096 ((INSTANCE) == TIM3) || \
14097 ((INSTANCE) == TIM4) || \
14098 ((INSTANCE) == TIM5) || \
14099 ((INSTANCE) == TIM6) || \
14100 ((INSTANCE) == TIM7) || \
14101 ((INSTANCE) == TIM8) || \
14102 ((INSTANCE) == TIM9) || \
14103 ((INSTANCE) == TIM10)|| \
14104 ((INSTANCE) == TIM11)|| \
14105 ((INSTANCE) == TIM12)|| \
14106 ((INSTANCE) == TIM13)|| \
14107 ((INSTANCE) == TIM14))
14108
14109/************* TIM Instances : at least 1 capture/compare channel *************/
14110#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14111 ((INSTANCE) == TIM2) || \
14112 ((INSTANCE) == TIM3) || \
14113 ((INSTANCE) == TIM4) || \
14114 ((INSTANCE) == TIM5) || \
14115 ((INSTANCE) == TIM8) || \
14116 ((INSTANCE) == TIM9) || \
14117 ((INSTANCE) == TIM10) || \
14118 ((INSTANCE) == TIM11) || \
14119 ((INSTANCE) == TIM12) || \
14120 ((INSTANCE) == TIM13) || \
14121 ((INSTANCE) == TIM14))
14122
14123/************ TIM Instances : at least 2 capture/compare channels *************/
14124#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14125 ((INSTANCE) == TIM2) || \
14126 ((INSTANCE) == TIM3) || \
14127 ((INSTANCE) == TIM4) || \
14128 ((INSTANCE) == TIM5) || \
14129 ((INSTANCE) == TIM8) || \
14130 ((INSTANCE) == TIM9) || \
14131 ((INSTANCE) == TIM12))
14132
14133/************ TIM Instances : at least 3 capture/compare channels *************/
14134#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14135 ((INSTANCE) == TIM2) || \
14136 ((INSTANCE) == TIM3) || \
14137 ((INSTANCE) == TIM4) || \
14138 ((INSTANCE) == TIM5) || \
14139 ((INSTANCE) == TIM8))
14140
14141/************ TIM Instances : at least 4 capture/compare channels *************/
14142#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14143 ((INSTANCE) == TIM2) || \
14144 ((INSTANCE) == TIM3) || \
14145 ((INSTANCE) == TIM4) || \
14146 ((INSTANCE) == TIM5) || \
14147 ((INSTANCE) == TIM8))
14148
14149/******************** TIM Instances : Advanced-control timers *****************/
14150#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14151 ((INSTANCE) == TIM8))
14152
14153/******************* TIM Instances : Timer input XOR function *****************/
14154#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14155 ((INSTANCE) == TIM2) || \
14156 ((INSTANCE) == TIM3) || \
14157 ((INSTANCE) == TIM4) || \
14158 ((INSTANCE) == TIM5) || \
14159 ((INSTANCE) == TIM8))
14160
14161/****************** TIM Instances : DMA requests generation (UDE) *************/
14162#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14163 ((INSTANCE) == TIM2) || \
14164 ((INSTANCE) == TIM3) || \
14165 ((INSTANCE) == TIM4) || \
14166 ((INSTANCE) == TIM5) || \
14167 ((INSTANCE) == TIM6) || \
14168 ((INSTANCE) == TIM7) || \
14169 ((INSTANCE) == TIM8))
14170
14171/************ TIM Instances : DMA requests generation (CCxDE) *****************/
14172#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14173 ((INSTANCE) == TIM2) || \
14174 ((INSTANCE) == TIM3) || \
14175 ((INSTANCE) == TIM4) || \
14176 ((INSTANCE) == TIM5) || \
14177 ((INSTANCE) == TIM8))
14178
14179/************ TIM Instances : DMA requests generation (COMDE) *****************/
14180#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14181 ((INSTANCE) == TIM2) || \
14182 ((INSTANCE) == TIM3) || \
14183 ((INSTANCE) == TIM4) || \
14184 ((INSTANCE) == TIM5) || \
14185 ((INSTANCE) == TIM8))
14186
14187/******************** TIM Instances : DMA burst feature ***********************/
14188#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14189 ((INSTANCE) == TIM2) || \
14190 ((INSTANCE) == TIM3) || \
14191 ((INSTANCE) == TIM4) || \
14192 ((INSTANCE) == TIM5) || \
14193 ((INSTANCE) == TIM8))
14194
14195/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
14196#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14197 ((INSTANCE) == TIM2) || \
14198 ((INSTANCE) == TIM3) || \
14199 ((INSTANCE) == TIM4) || \
14200 ((INSTANCE) == TIM5) || \
14201 ((INSTANCE) == TIM6) || \
14202 ((INSTANCE) == TIM8))
14203
14204/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14205#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14206 ((INSTANCE) == TIM2) || \
14207 ((INSTANCE) == TIM3) || \
14208 ((INSTANCE) == TIM4) || \
14209 ((INSTANCE) == TIM5) || \
14210 ((INSTANCE) == TIM8) || \
14211 ((INSTANCE) == TIM9) || \
14212 ((INSTANCE) == TIM12))
14213/********************** TIM Instances : 32 bit Counter ************************/
14214#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
14215 ((INSTANCE) == TIM5))
14216
14217/***************** TIM Instances : external trigger input available ************/
14218#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14219 ((INSTANCE) == TIM2) || \
14220 ((INSTANCE) == TIM3) || \
14221 ((INSTANCE) == TIM4) || \
14222 ((INSTANCE) == TIM5) || \
14223 ((INSTANCE) == TIM8))
14224
14225/****************** TIM Instances : remapping capability **********************/
14226#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
14227 ((INSTANCE) == TIM5) || \
14228 ((INSTANCE) == TIM11))
14229
14230/******************* TIM Instances : output(s) available **********************/
14231#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14232 ((((INSTANCE) == TIM1) && \
14233 (((CHANNEL) == TIM_CHANNEL_1) || \
14234 ((CHANNEL) == TIM_CHANNEL_2) || \
14235 ((CHANNEL) == TIM_CHANNEL_3) || \
14236 ((CHANNEL) == TIM_CHANNEL_4))) \
14237 || \
14238 (((INSTANCE) == TIM2) && \
14239 (((CHANNEL) == TIM_CHANNEL_1) || \
14240 ((CHANNEL) == TIM_CHANNEL_2) || \
14241 ((CHANNEL) == TIM_CHANNEL_3) || \
14242 ((CHANNEL) == TIM_CHANNEL_4))) \
14243 || \
14244 (((INSTANCE) == TIM3) && \
14245 (((CHANNEL) == TIM_CHANNEL_1) || \
14246 ((CHANNEL) == TIM_CHANNEL_2) || \
14247 ((CHANNEL) == TIM_CHANNEL_3) || \
14248 ((CHANNEL) == TIM_CHANNEL_4))) \
14249 || \
14250 (((INSTANCE) == TIM4) && \
14251 (((CHANNEL) == TIM_CHANNEL_1) || \
14252 ((CHANNEL) == TIM_CHANNEL_2) || \
14253 ((CHANNEL) == TIM_CHANNEL_3) || \
14254 ((CHANNEL) == TIM_CHANNEL_4))) \
14255 || \
14256 (((INSTANCE) == TIM5) && \
14257 (((CHANNEL) == TIM_CHANNEL_1) || \
14258 ((CHANNEL) == TIM_CHANNEL_2) || \
14259 ((CHANNEL) == TIM_CHANNEL_3) || \
14260 ((CHANNEL) == TIM_CHANNEL_4))) \
14261 || \
14262 (((INSTANCE) == TIM8) && \
14263 (((CHANNEL) == TIM_CHANNEL_1) || \
14264 ((CHANNEL) == TIM_CHANNEL_2) || \
14265 ((CHANNEL) == TIM_CHANNEL_3) || \
14266 ((CHANNEL) == TIM_CHANNEL_4))) \
14267 || \
14268 (((INSTANCE) == TIM9) && \
14269 (((CHANNEL) == TIM_CHANNEL_1) || \
14270 ((CHANNEL) == TIM_CHANNEL_2))) \
14271 || \
14272 (((INSTANCE) == TIM10) && \
14273 (((CHANNEL) == TIM_CHANNEL_1))) \
14274 || \
14275 (((INSTANCE) == TIM11) && \
14276 (((CHANNEL) == TIM_CHANNEL_1))) \
14277 || \
14278 (((INSTANCE) == TIM12) && \
14279 (((CHANNEL) == TIM_CHANNEL_1) || \
14280 ((CHANNEL) == TIM_CHANNEL_2))) \
14281 || \
14282 (((INSTANCE) == TIM13) && \
14283 (((CHANNEL) == TIM_CHANNEL_1))) \
14284 || \
14285 (((INSTANCE) == TIM14) && \
14286 (((CHANNEL) == TIM_CHANNEL_1))))
14287
14288/************ TIM Instances : complementary output(s) available ***************/
14289#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14290 ((((INSTANCE) == TIM1) && \
14291 (((CHANNEL) == TIM_CHANNEL_1) || \
14292 ((CHANNEL) == TIM_CHANNEL_2) || \
14293 ((CHANNEL) == TIM_CHANNEL_3))) \
14294 || \
14295 (((INSTANCE) == TIM8) && \
14296 (((CHANNEL) == TIM_CHANNEL_1) || \
14297 ((CHANNEL) == TIM_CHANNEL_2) || \
14298 ((CHANNEL) == TIM_CHANNEL_3))))
14299
14300/****************** TIM Instances : supporting counting mode selection ********/
14301#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14302 ((INSTANCE) == TIM2) || \
14303 ((INSTANCE) == TIM3) || \
14304 ((INSTANCE) == TIM4) || \
14305 ((INSTANCE) == TIM5) || \
14306 ((INSTANCE) == TIM8))
14307
14308/****************** TIM Instances : supporting clock division *****************/
14309#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14310 ((INSTANCE) == TIM2) || \
14311 ((INSTANCE) == TIM3) || \
14312 ((INSTANCE) == TIM4) || \
14313 ((INSTANCE) == TIM5) || \
14314 ((INSTANCE) == TIM8) || \
14315 ((INSTANCE) == TIM9) || \
14316 ((INSTANCE) == TIM10)|| \
14317 ((INSTANCE) == TIM11)|| \
14318 ((INSTANCE) == TIM12)|| \
14319 ((INSTANCE) == TIM13)|| \
14320 ((INSTANCE) == TIM14))
14321
14322/****************** TIM Instances : supporting commutation event generation ***/
14323#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
14324 ((INSTANCE) == TIM8))
14325
14326
14327/****************** TIM Instances : supporting OCxREF clear *******************/
14328#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14329 ((INSTANCE) == TIM2) || \
14330 ((INSTANCE) == TIM3) || \
14331 ((INSTANCE) == TIM4) || \
14332 ((INSTANCE) == TIM5) || \
14333 ((INSTANCE) == TIM8))
14334
14335/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
14336#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14337 ((INSTANCE) == TIM2) || \
14338 ((INSTANCE) == TIM3) || \
14339 ((INSTANCE) == TIM4) || \
14340 ((INSTANCE) == TIM5) || \
14341 ((INSTANCE) == TIM8) || \
14342 ((INSTANCE) == TIM9) || \
14343 ((INSTANCE) == TIM12))
14344
14345/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
14346#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14347 ((INSTANCE) == TIM2) || \
14348 ((INSTANCE) == TIM3) || \
14349 ((INSTANCE) == TIM4) || \
14350 ((INSTANCE) == TIM5) || \
14351 ((INSTANCE) == TIM8))
14352
14353/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
14354#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14355 ((INSTANCE) == TIM2) || \
14356 ((INSTANCE) == TIM3) || \
14357 ((INSTANCE) == TIM4) || \
14358 ((INSTANCE) == TIM5) || \
14359 ((INSTANCE) == TIM8) || \
14360 ((INSTANCE) == TIM9) || \
14361 ((INSTANCE) == TIM12))
14362
14363/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
14364#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14365 ((INSTANCE) == TIM2) || \
14366 ((INSTANCE) == TIM3) || \
14367 ((INSTANCE) == TIM4) || \
14368 ((INSTANCE) == TIM5) || \
14369 ((INSTANCE) == TIM8) || \
14370 ((INSTANCE) == TIM9) || \
14371 ((INSTANCE) == TIM12))
14372
14373/****************** TIM Instances : supporting repetition counter *************/
14374#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14375 ((INSTANCE) == TIM8))
14376
14377/****************** TIM Instances : supporting encoder interface **************/
14378#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14379 ((INSTANCE) == TIM2) || \
14380 ((INSTANCE) == TIM3) || \
14381 ((INSTANCE) == TIM4) || \
14382 ((INSTANCE) == TIM5) || \
14383 ((INSTANCE) == TIM8) || \
14384 ((INSTANCE) == TIM9) || \
14385 ((INSTANCE) == TIM12))
14386/****************** TIM Instances : supporting Hall sensor interface **********/
14387#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14388 ((INSTANCE) == TIM2) || \
14389 ((INSTANCE) == TIM3) || \
14390 ((INSTANCE) == TIM4) || \
14391 ((INSTANCE) == TIM5) || \
14392 ((INSTANCE) == TIM8))
14393/****************** TIM Instances : supporting the break function *************/
14394#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14395 ((INSTANCE) == TIM8))
14396
14397/******************** USART Instances : Synchronous mode **********************/
14398#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14399 ((INSTANCE) == USART2) || \
14400 ((INSTANCE) == USART3) || \
14401 ((INSTANCE) == USART6))
14402
14403/******************** UART Instances : Half-Duplex mode **********************/
14404#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14405 ((INSTANCE) == USART2) || \
14406 ((INSTANCE) == USART3) || \
14407 ((INSTANCE) == USART6))
14408
14409/* Legacy defines */
14410#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
14411
14412/****************** UART Instances : Hardware Flow control ********************/
14413#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14414 ((INSTANCE) == USART2) || \
14415 ((INSTANCE) == USART3))
14416/******************** UART Instances : LIN mode **********************/
14417#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
14418
14419/********************* UART Instances : Smart card mode ***********************/
14420#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14421 ((INSTANCE) == USART2) || \
14422 ((INSTANCE) == USART3) || \
14423 ((INSTANCE) == USART6))
14424
14425/*********************** UART Instances : IRDA mode ***************************/
14426#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14427 ((INSTANCE) == USART2) || \
14428 ((INSTANCE) == USART3) || \
14429 ((INSTANCE) == USART6))
14430
14431/*********************** PCD Instances ****************************************/
14432#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
14433
14434/*********************** HCD Instances ****************************************/
14435#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
14436
14437/****************************** SDIO Instances ********************************/
14438#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
14439
14440/****************************** IWDG Instances ********************************/
14441#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14442
14443/****************************** WWDG Instances ********************************/
14444#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
14445
14446
14447/***************************** FMPI2C Instances *******************************/
14448#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
14449#define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
14450
14451/****************************** QSPI Instances ********************************/
14452#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
14453/****************************** USB Exported Constants ************************/
14454#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
14455#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
14456#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
14457#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
14458
14459/*
14460 * @brief Specific devices reset values definitions
14461 */
14462#define RCC_PLLCFGR_RST_VALUE 0x24003010U
14463#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
14464
14465#define RCC_MAX_FREQUENCY 100000000U
14466#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
14467#define RCC_MAX_FREQUENCY_SCALE2 84000000U
14468#define RCC_MAX_FREQUENCY_SCALE3 64000000U
14469#define RCC_PLLVCO_OUTPUT_MIN 100000000U
14470#define RCC_PLLVCO_INPUT_MIN 950000U
14471#define RCC_PLLVCO_INPUT_MAX 2100000U
14472#define RCC_PLLVCO_OUTPUT_MAX 432000000U
14473
14474#define RCC_PLLN_MIN_VALUE 50U
14475#define RCC_PLLN_MAX_VALUE 432U
14476
14477#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
14478#define FLASH_SCALE1_LATENCY2_FREQ 64000000U
14479#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
14480
14481#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
14482#define FLASH_SCALE2_LATENCY2_FREQ 64000000U
14483
14484#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
14485#define FLASH_SCALE3_LATENCY2_FREQ 64000000U
14486
14487/******************************************************************************/
14488/* For a painless codes migration between the STM32F4xx device product */
14489/* lines, the aliases defined below are put in place to overcome the */
14490/* differences in the interrupt handlers and IRQn definitions. */
14491/* No need to update developed interrupt code when moving across */
14492/* product lines within the same STM32F4 Family */
14493/******************************************************************************/
14494/* Aliases for __IRQn */
14495#define FMC_IRQn FSMC_IRQn
14496
14497/* Aliases for __IRQHandler */
14498#define FMC_IRQHandler FSMC_IRQHandler
14499
14503
14507
14511
14512#ifdef __cplusplus
14513}
14514#endif /* __cplusplus */
14515
14516#endif /* __STM32F412Vx_H */
#define __IO
#define RESERVED(N, T)
Definition core_ca.h:179
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f401xc.h:66
@ PendSV_IRQn
Definition stm32f401xc.h:74
@ EXTI2_IRQn
Definition stm32f401xc.h:85
@ DMA1_Stream2_IRQn
Definition stm32f401xc.h:90
@ CAN1_SCE_IRQn
Definition stm32f405xx.h:99
@ SDIO_IRQn
@ RTC_WKUP_IRQn
Definition stm32f401xc.h:80
@ DMA2_Stream0_IRQn
@ DMA2_Stream6_IRQn
@ I2C1_ER_IRQn
@ I2C2_EV_IRQn
@ MemoryManagement_IRQn
Definition stm32f401xc.h:69
@ TIM4_IRQn
@ TIM2_IRQn
@ DMA2_Stream7_IRQn
@ TIM8_BRK_TIM12_IRQn
@ USART2_IRQn
@ DMA2_Stream3_IRQn
@ SVCall_IRQn
Definition stm32f401xc.h:72
@ ADC_IRQn
Definition stm32f401xc.h:95
@ SPI3_IRQn
@ SPI2_IRQn
@ TIM7_IRQn
@ CAN2_SCE_IRQn
@ RCC_IRQn
Definition stm32f401xc.h:82
@ I2C2_ER_IRQn
@ QUADSPI_IRQn
@ DFSDM1_FLT0_IRQn
@ TIM8_CC_IRQn
@ UsageFault_IRQn
Definition stm32f401xc.h:71
@ SysTick_IRQn
Definition stm32f401xc.h:75
@ I2C3_ER_IRQn
@ FMPI2C1_ER_IRQn
@ I2C3_EV_IRQn
@ CAN2_RX0_IRQn
@ BusFault_IRQn
Definition stm32f401xc.h:70
@ SPI5_IRQn
@ DebugMonitor_IRQn
Definition stm32f401xc.h:73
@ RNG_IRQn
@ FLASH_IRQn
Definition stm32f401xc.h:81
@ DMA2_Stream5_IRQn
@ WWDG_IRQn
Definition stm32f401xc.h:77
@ I2C1_EV_IRQn
@ TIM3_IRQn
@ DMA2_Stream1_IRQn
@ TIM6_IRQn
@ CAN1_TX_IRQn
Definition stm32f405xx.h:96
@ DMA1_Stream0_IRQn
Definition stm32f401xc.h:88
@ EXTI15_10_IRQn
@ SPI4_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f401xc.h:98
@ EXTI9_5_IRQn
Definition stm32f401xc.h:96
@ DMA1_Stream1_IRQn
Definition stm32f401xc.h:89
@ OTG_FS_IRQn
@ OTG_FS_WKUP_IRQn
@ FPU_IRQn
@ TIM8_UP_TIM13_IRQn
@ USART6_IRQn
@ SPI1_IRQn
@ PVD_IRQn
Definition stm32f401xc.h:78
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f401xc.h:99
@ TIM1_BRK_TIM9_IRQn
Definition stm32f401xc.h:97
@ CAN2_RX1_IRQn
@ EXTI0_IRQn
Definition stm32f401xc.h:83
@ CAN1_RX0_IRQn
Definition stm32f405xx.h:97
@ EXTI4_IRQn
Definition stm32f401xc.h:87
@ DMA2_Stream2_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f401xc.h:79
@ DMA1_Stream5_IRQn
Definition stm32f401xc.h:93
@ USART1_IRQn
@ EXTI3_IRQn
Definition stm32f401xc.h:86
@ NonMaskableInt_IRQn
Definition stm32f401xc.h:68
@ TIM8_TRG_COM_TIM14_IRQn
@ EXTI1_IRQn
Definition stm32f401xc.h:84
@ DMA2_Stream4_IRQn
@ FMPI2C1_EV_IRQn
@ TIM5_IRQn
@ DMA1_Stream7_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f401xc.h:92
@ DMA1_Stream6_IRQn
Definition stm32f401xc.h:94
@ TIM1_CC_IRQn
@ CAN2_TX_IRQn
@ CAN1_RX1_IRQn
Definition stm32f405xx.h:98
@ DMA1_Stream3_IRQn
Definition stm32f401xc.h:91
@ USART3_IRQn
@ RTC_Alarm_IRQn
@ DFSDM1_FLT1_IRQn
Analog to Digital Converter.
Controller Area Network FIFOMailBox.
Controller Area Network FilterRegister.
Controller Area Network TxMailBox.
Controller Area Network.
CRC calculation unit.
Debug MCU.
DFSDM channel configuration registers.
DFSDM module registers.
DMA Controller.
External Interrupt/Event Controller.
FLASH Registers.
Inter-integrated Circuit Interface.
Flexible Static Memory Controller.
Flexible Static Memory Controller Bank1E.
General Purpose I/O.
Inter-integrated Circuit Interface.
Independent WATCHDOG.
Power Control.
QUAD Serial Peripheral Interface.
Reset and Clock Control.
Real-Time Clock.
SD host Interface.
Serial Peripheral Interface.
System configuration controller.
Universal Synchronous Asynchronous Receiver Transmitter.
USB_OTG_device_Registers.
USB_OTG_Core_Registers.
USB_OTG_Host_Channel_Specific_Registers.
USB_OTG_Host_Mode_Register_Structures.
USB_OTG_IN_Endpoint-Specific_Register.
USB_OTG_OUT_Endpoint-Specific_Registers.
Window WATCHDOG.
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.